ISL9003AIECZ-T datasheet(8/12 Pages) INTERSIL

Part #	ISL9003AIECZ-T

Description	Low Noise LDO with Low IQ and High PSRR

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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8 / 12 page

8

FN6299.5

July 18, 2014

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Pin Description

Typical Application

5 LD SC-70

NUMBER

6 LD µTDFN

NUMBER

PIN NAME

DESCRIPTION

16

VIN

Supply Voltage/LDO Input. Connect a 1µF capacitor to GND.

2

GND

GND is the connection to system ground. Connect to PCB Ground plane.

3

4

EN

Output Enable. When this signal goes high, the LDO is turned on.

4

3

CBYP

Reference Bypass Capacitor Pin. Optionally connect capacitor of value 0.01µF to 1µF between this pin

and GND to tune in the desired noise and PSRR performance.

51

VO

LDO Output. Connect a 1µF capacitor of value to GND.

-

5

NC

No Connect.

C1, C2: 1µF X5R CERAMIC CAPACITOR

ISL9003A (SC-70)

VIN

GND

VO

CBYP

5

4

1

2

VIN (2.3V TO 5V)

VOUT

C1

C2

EN

3

ENABLE

OFF

ON

C3

C3: 0.1µF X5R CERAMIC CAPACITOR

C1, C2: 1µF X5R CERAMIC CAPACITOR

ISL9003A (µTDFN)

VO

GND

VIN

EN

5

4

1

2

VOUT

C1

C2

CBYP

3

ENABLE

OFF

ON

C3

C3: 0.1µF X5R CERAMIC CAPACITOR

NC

VIN (2.3V TO 5V)

6

ISL9003A

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ISL9003AIECZ-T Datasheet(PDF) 8 Page - Intersil Corporation

ISL9003AIECZ-T Datasheet(HTML) 8 Page - Intersil Corporation

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