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AD7278BRMZ-REEL Datasheet(PDF) 13 Page - Analog Devices |
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AD7278BRMZ-REEL Datasheet(HTML) 13 Page - Analog Devices |
13 / 29 page AD7276/AD7277/AD7278 Rev. C | Page 12 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 GND 2 VIN 3 CS 6 SCLK 4 SDATA 5 AD7276/ AD7277/ AD7278 TOP VIEW (Not to Scale) Figure 8. 6-Lead TSOT Pin Configuration VDD 1 SDATA 2 CS 3 NC 4 VIN 8 GND 7 SCLK 6 NC 5 NC = NO CONNECT AD7276/ AD7277/ AD7278 TOP VIEW (Not to Scale) Figure 9. 8-Lead MSOP Pin Configuration Table 7. Pin Function Descriptions Pin No. 6-Lead TSOT 8-Lead MSOP Mnemonic Description 1 1 VDD Power Supply Input. The VDD range for the AD7276/AD7277/AD7278 is 2.35 V to 3.6 V. 2 7 GND Analog Ground. Ground reference point for all circuitry on the AD7276/AD7277/AD7278. All analog input signals should be referred to this GND voltage. 3 8 VIN Analog Input. Single-ended analog input channel. The input range is 0 V to VDD. 4 6 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7276/AD7277/AD7278. 5 2 SDATA Data Out. Logic output. The conversion result from the AD7276/AD7277/AD7278 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7276 consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros, provided MSB first. The data stream from the AD7277 consists of two leading zeros followed by 10 bits of conversion data and four trailing zeros, provided MSB first. The data stream from the AD7278 consists of two leading zeros followed by 8 bits of conversion data and six trailing zeros, provided MSB first. 6 3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversion on the AD7276/AD7277/AD7278 and framing the serial data transfer. 4, 5 NC No Connect. |
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