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AD7278BRMZ Datasheet(PDF) 25 Page - Analog Devices

Part No. AD7278BRMZ
Description  3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7278BRMZ Datasheet(HTML) 25 Page - Analog Devices

 
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AD7276/AD7277/AD7278
Rev. C | Page 24 of 28
AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE
For the AD7278, if CS is brought high during the 10
th rising
edge after the two leading zeros and eight bits of the conversion
are provided, then the part can achieve a 4 MSPS throughput
rate. For the AD7278, the track-and-hold goes back into track
mode on the ninth rising edge. In this case, a fSCLK = 48 MHz and
throughput of 4 MSPS result in a cycle time of t2 + 8.5(1/fSCLK) +
tACQ = 250 ns, where t2 = 6 ns minimum and tACQ = 67 ns. This
satisfies the requirement of 60 ns for tACQ.
shows that
tACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where t8 = 14 ns max.
This allows a value of 43 ns for tQUIET, satisfying the minimum
requirement of 4 ns.
Figure 35
MICROPROCESSOR INTERFACING
AD7276/AD7277/AD7278-to-ADSP-BF53x
The ADSP-BF53x family of DSPs interfaces directly to the
AD7276/AD7277/AD7278 without requiring glue logic. The
SPORT0 Receive Configuration 1 Register should be set up as
outlined in Table 9.
AD7276/
AD7277/
AD7278*
ADSP-BF53x*
SCLK
RCLK0
SPORT0
DR0PRI
RFS0
DT0
DOUT
CS
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 36. Interfacing with ADSP-BF53x
Table 9. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
Setting
Description
RCKFE = 1
Sample data with falling edge of RSCLK
LRFS = 1
Active low frame signal
RFSR = 1
Frame every word
IRFS = 1
Internal RFS used
RLSBIT = 0
Receive MSB first
RDTYPE = 00
Zero fill
IRCLK = 1
Internal receive clock
RSPEN = 1
Receive enabled
SLEN = 1111
16-bit data-word (or can be set to 1101 for
14-bit data-word)
TFSR = RFSR = 1
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.


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