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AD7278BRMZ Datasheet(PDF) 23 Page - Analog Devices |
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AD7278BRMZ Datasheet(HTML) 23 Page - Analog Devices |
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23 / 29 page 
AD7276/AD7277/AD7278 Rev. C | Page 22 of 28 SERIAL INTERFACE Figure 31 through Figure 34 show the detailed timing diagrams for serial interfacing to the AD7276, AD7277, and AD7278. The serial clock provides the conversion clock and controls the transfer of information from the AD7276/AD7277/AD7278 during conversion. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode and takes the bus out of three-state. The analog input is sampled and the conversion is initiated at this point. For the AD7276, the conversion requires completing 14 SCLK cycles. Once 13 SCLK falling edges have elapsed, the track-and- hold goes back into track mode on the next SCLK rising edge, as shown in Figure 31 at Point B. If the rising edge of CS occurs before 14 SCLKs have elapsed, the conversion is terminated and the SDATA line goes back into three-state. If 16 SCLKs are considered in the cycle, the last two bits are zeros and SDATA returns to three-state on the 16th SCLK falling edge, as shown in . Figure 32 For the AD7277, the conversion requires completing 12 SCLK cycles. Once 11 SCLK falling edges elapse, the track-and-hold goes back into track mode on the next SCLK rising edge, as shown in Figure 33 at Point B. If the rising edge of CS occurs before 12 SCLKs elapse, the conversion is terminated and the SDATA line goes back into three-state. If 16 SCLKs are considered in the cycle, the AD7277 clocks out four trailing zeros for the last four bits and SDATA returns to three-state on the 16th SCLK falling edge, as shown in . Figure 33 For the AD7278, the conversion requires completing 10 SCLK cycles. Once 9 SCLK falling edges elapse, the track-and-hold goes back into track mode on the next rising edge. If the rising edge of CS occurs before 10 SCLKs elapse, the part enters power- down mode. If 16 SCLKs are considered in the cycle, then the AD7278 clocks out six trailing zeros for the last six bits and SDATA returns to three-state on the 16th SCLK falling edge, as shown in Figure 34. If the user considers a 14 SCLK cycle serial interface for the AD7276/AD7277/AD7278, then CS must be brought high after the 14th SCLK falling edge. Then the last two trailing zeros are ignored, and SDATA goes back into three-state. In this case, the 3 MSPS throughput can be achieved by using a 48 MHz clock frequency. CS going low clocks out the first leading zero to be read by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with the second leading zero. Therefore, the first falling clock edge on the serial clock provides the first leading zero and clocks out the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, because it is clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it is possible to read data on each SCLK rising edge. In such cases, the first falling edge of SCLK clocks out the second leading zero and can be read on the first rising edge. However, the first leading zero clocked out when CS goes low is missed if read within the first falling edge. The 15th falling edge of SCLK clocks out the last bit and can be read on the 15th rising SCLK edge. If CS goes low just after one SCLK falling edge elapses, then CS clocks out the first leading zero and can be read on the SCLK rising edge. The next SCLK falling edge clocks out the second leading zero and can be read on the following rising edge. tQUIET tCONVERT 1/THROUGHPUT CS 15 13 t4 23 4 t5 t3 t2 t6 t7 t9 14 B t1 SCLK SDATA THREE-STATE THREE- STATE 2 LEADING ZEROS ZZERO DB11 DB10 DB9 DB1 DB0 Figure 31. AD7276 Serial Interface Timing Diagram 14 SCLK Cycle |
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