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AD7278BRMZ Datasheet(PDF) 9 Page - Analog Devices

Part No. AD7278BRMZ
Description  3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7278BRMZ Datasheet(HTML) 9 Page - Analog Devices

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AD7276/AD7277/AD7278
Rev. C | Page 8 of 28
Parameter
A Grade1, 2
B Grade1, 2
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.35/3.6
2.35/3.6
V min/max
IDD
Digital I/Ps = 0 V or VDD
Normal Mode (Static)
0.5
0.5
mA typ
VDD = 3.6 V, SCLK on or off
Normal Mode (Operational)
5.5
5.5
mA max
VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS
3.5
3.5
mA typ
VDD = 3 V
Partial Power-Down Mode (Static)
34
34
μA typ
Full Power-Down Mode (Static)
2
2
μA max
−40°C to +85°C, typically 0.1 μA
10
10
μA max
+85°C to +125°C
Power Dissipation5
Normal Mode (Operational)
19.8
19.8
mW max
VDD = 3.6 V, fSAMPLE = 3 MSPS
10.5
10.5
mW typ
VDD = 3 V
Partial Power-Down
102
102
μW typ
VDD = 3 V
Full Power-Down
7.2
7.2
μW max
VDD = 3.6 V, −40°C to +85°C
1 Temperature range from −40°C to +125°C.
2 Typical specifications are tested with VDD = 3 V and at 25°C.
3 See the Terminology section.
4 Guaranteed by characterization.
5 See the Power vs. Throughput Rate section.
TIMING SPECIFICATIONS—AD7276/AD7277/AD7278
VDD = 2.35 V to 3.6 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter2
Limit at TMIN, TMAX
Unit
Description
fSCLK3
500
kHz min4
48
MHz max
B grade
16
MHz max
Y grade
tCONVERT
14 × tSCLK
AD7276
12 × tSCLK
AD7277
10 × tSCLK
AD7278
tQUIET
4
ns min
Minimum quiet time required between the bus relinquish and the
start of the next conversion
t1
3
ns min
Minimum CS pulse width
t2
6
ns min
CS to SCLK setup time
t35
4
ns max
Delay from CS until SDATA three-state disabled
t45
15
ns max
Data access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK low pulse width
t6
0.4 tSCLK
ns min
SCLK high pulse width
t75
5
ns min
SCLK to data valid hold time
t8
14
ns max
SCLK falling edge to SDATA three-state
5
ns min
SCLK falling edge to SDATA three-state
t9
4.2
ns max
CS rising edge to SDATA three-state
TPOWER-UP6
1
μs max
Power-up time from full power-down
1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this
value, a digital buffer or latch must be used.
2 Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
3 Mark/space ratio for the SCLK input is 40/60 to 60/40.
4 Minimum fSCLK at which specifications are guaranteed.
5 The time required for the output to cross the VIH or VIL voltage.
6 See the Power-Up Times section.


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