3-137

80C286/883

NOTES:

1. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus operation

will be either a memory read at operand address or I/O read at port address 00FA(H).

2. To prevent a second processor extension data operand transfer, the worst case maximum time (shown above) is 3 x

The actual, configuration dependent, maximum time is: 3 x

(4)

to either the first or second bus operation of the processor extension data operand transfer sequence.

FIGURE 6. 80C286/883 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY

NOTES:

1. Setup time for RESET

↑ may be violated with the consideration that φ1 of the processor clock may begin one system CLK period later.

2. Setup and hold times for RESET

↓ must be met for proper operation, but RESET ↓ may occur during φ1 or φ2.

3. The data bus is only guaranteed to be in a high impedance state at the time shown.

FIGURE 7. INITIAL 80C286/883 PIN STATE DURING RESET

1

12A

φ2

CLK

φ1

φ2

φ2

φ1

φ2

φ1

φ1

φ2

CLK

S1 • S0

PEACK

M/IO,

COD INTA

PEREQ

MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O

PORT ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER

12B

5

4

I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER

MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER

BUS CYCLE TYPE

(SEE NOTE 1)

(SEE NOTE 2)

I/0 READ IF PROC. EXT. TO MEMORY

MEMORY READ IF MEMORY TO PROC. EXT

MEMORY WRITE IF PROC. EXT. TO MEMORY

I/O WRITE IF MEMORY TO PROC. EXT.

1

1

12B

S1 • S0

BUS CYCLE TYPE

φ2

φ2

φ2

φ2

φ2

φ1

φ1

φ1

φ1

CLK

6

7

6

(SEE NOTE 1)

PEACK

BHE

M/IO

COD/INTA

AT LEAST

16 CLK PERIODS

UNKNOWN

UNKNOWN

UNKNOWN

UNKNOWN

UNKNOWN

13

13

13

15

(SEE NOTE 3)

LOCK

DATA

HILDA

16

(SEE NOTE 2)

RESET