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82C237 Datasheet(PDF) 3 Page - Intersil Corporation

Part No. 82C237
Description  CMOS High Performance Programmable DMA Controller
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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4-150
82C237
Pin Description
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
VCC
31
VCC: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for
decoupling.
GND
20
Ground
CLK
12
I
CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C237
operations. This input may be driven from DC to 12.5MHz for the 82C237-12 or from DC to 8MHz
for the 82C237. The Clock may be stopped in either state for standby operation.
CS
11
I
CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for
CPU communications.
RESET
13
I
RESET: This is an active high input which clears the Command, Status, Request, and Temporary
registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore
requests. The Data-Width register is set to perform 8-bit transfers on all channels (82C237 only).
Following a Reset, the controller is in an idle cycle.
READY
6
I
READY: This signal can be used to extend the memory read and write pulses from the 82C237 to
accommodate slow memories or I/O devices. READY must not make transitions during its specified
set-up and hold times. See Figure 14 for timing. READY is ignored in verify transfer mode.
HLDA
7
I
HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has
relinquished control of the system busses. HLDA is a synchronous input and must not transition
during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising
edge of clock, during which time HLDA must not transition.
DREQ0-
DREQ3
16-19
I
DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request
inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest
priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a
channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is
programmable. RESET initializes these lines to active high. DREQ must be maintained until the
corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused
DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set. In 16-bit
Transfer mode (82C237 only), each DREQ channel may be programmed to perform either 8-bit or
16-bit DMA transfers.
DB0-DB7
21-23
26-30
I/O
DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data
bus. The outputs are enabled in the Program condition during the I/O Read to output the contents
of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle
when the CPU is programming the 82C237 control registers. During DMA cycles, the most signifi-
cant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB.
In memory-to-memory operations, data from the memory enters the 82C237 on the data bus during
the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write
the data into the new memory location.
IOR
1
I/O
I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control
signal used by the 82C237 to access data from the peripheral during a DMA Write transfer.
IOW
2
I/O
I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to load information into the 82C237. In the Active cycle, it is an output
control signal used by the 82C237 to load data to the peripheral during a DMA Read transfer.




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