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AD5678 Datasheet(PDF) 24 Page - Analog Devices |
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AD5678 Datasheet(HTML) 24 Page - Analog Devices |
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24 / 28 page 
AD5678 Rev. C | Page 24 of 28 Table 9. Internal Reference Register Internal REF Register (DB0) Action 0 Reference off (default) 1 Reference on Table 10. 32-Bit Input Shift Register Contents for Reference Set-Up Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB1 DB0 X 1 0 0 0 X X X X X 1/0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares Internal REF register Table 11. Power-Down Modes of Operation DB9 DB8 Operating Mode 0 0 Normal operation Power-down modes 0 1 1 kΩ to GND 1 0 100 kΩ to GND 1 1 Three-state Table 12. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X 0 1 0 0 X X X X X PD1 PD0 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)— don’t cares Don’t cares Power- down mode Power-down/power-up channel selection—set bit to 1 to select RESISTOR NETWORK VOUT VFB RESISTOR STRING DAC POWER-DOWN CIRCUITRY AMPLIFIER Figure 50. Output Stage During Power-Down Table 13. Clear Code Register Clear Code Register DB1 DB0 CR1 CR0 Clears to Code 0 0 0x0000 0 1 0x8000 1 0 0xFFFF 1 1 No operation Table 14. 32-Bit Input Shift Register Contents for Clear Code Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 X 0 1 0 1 X X X X X CR1 CR0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Clear code register |
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