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AD5678 Datasheet(PDF) 8 Page - Analog Devices

Part No. AD5678
Description  On-Chip Reference in 14-Lead TSSOP
Download  28 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5678 Datasheet(HTML) 8 Page - Analog Devices

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AD5678
Rev. C | Page 8 of 28
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 5.5 V
Unit
Conditions/Comments
t1 1
20
ns min
SCLK cycle time
t2
8
ns min
SCLK high time
t3
8
ns min
SCLK low time
t4
13
ns min
SYNC to SCLK falling edge set-up time
t5
4
ns min
Data set-up time
t6
4
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
15
ns min
Minimum SYNC high time
t9
13
ns min
SYNC rising edge to SCLK fall ignore
t10
0
ns min
SCLK falling edge to SYNC fall ignore
t11
10
ns min
LDAC pulse width low
t12
15
ns min
SCLK falling edge to LDAC rising edge
t13
5
ns min
CLR pulse width low
t14
0
ns min
SCLK falling edge to LDAC falling edge
t15
300
ns typ
CLR pulse activation time
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
t4
t3
SCLK
SYNC
DIN
t1
t2
t5
t6
t7
t8
DB31
t9
t10
t11
t12
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
CLR
t13
t15
VOUT
DB0
LDAC1
LDAC2
Figure 2. Serial Write Operation


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