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M82380 Datasheet(PDF) 62 Page - Intel Corporation

Part # M82380
Description  HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

M82380 Datasheet(HTML) 62 Page - Intel Corporation

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M82380
Since the external Slave Cascade Address is provid-
ed on the Data Bus during INTA cycle 1 an external
latch is required to capture this address for the Slave
Controller A simple scheme is depicted in Figure 41
SPECIAL FULLY NESTED MODE
This mode will be used where cascading is em-
ployed and the priority is to be conserved within
each Slave Controller The Special Fully Nested
Mode is similar to the ‘regular’ Fully Nested Mode
with the following exceptions
When an interrupt request from a Slave Control-
ler is in service this Slave Controller is not
locked out from the Master’s priority logic Fur-
ther interrupt requests from the higher priority
logic within the Slave Controller will be recog-
nized by the M82380 PIC and will initiate inter-
rupts to the i386 processor In comparing to the
‘regular’ Fully Nested Mode the Slave Controller
is masked out when its request is in service and
no higher requests from the same Slave Control-
ler can be serviced
Before exiting the interrupt service routine the
software has to check whether the interrupt serv-
iced was the only request from the Slave Con-
troller This is done by sending a Non-Specific
EOI Command to the Slave Controller and then
reading its In Service Register If there are no
requests in the Slave Controller a Non-Specific
EOI can be sent to the corresponding M82380
PIC bank also Otherwise no EOI should be
sent
446 READING INTERRUPT STATUS
The M82380 PIC provides several ways to read dif-
ferent status of each interrupt bank for more flexible
interrupt control operations These include polling
the highest priority pending interrupt request and
reading the contents of different interrupt status reg-
isters
POLL COMMAND
The M82380 PIC supports status polling operations
with the Poll Command In a Poll Command the
pending interrupt request with the highest priority
can be determined To use this command the INT
output is not used or the i386 processor interrupt is
disabled Service to devices is achieved by software
using the Poll Command
This mode is useful if there is a routine command
common to several levels so that the INTA se-
quence is not needed Another application is to use
the Poll Command to expand the number of priority
levels
Notice that the ICW2 mechanism is not supported
for the Poll Command However if the Poll Com-
mand is used the programmable Vector Registers
are of no concern since no INTA cycle will be gener-
ated
READING INTERRUPT REGISTERS
The contents of each interrupt register (IRR ISR
and IMR) can be read to update the user’s program
on the present status of the M82380 PIC This can
be a versatile tool in the decision making process of
a service routine giving the user more control over
interrupt operations
The reading of the IRR and ISR contents can be
performed via the Operation Control Word 3 by us-
ing a Read Status Register Command and the con-
tent of IMR can be read via a simple read operation
of the register itself
45 Register Set Overview
Each bank of the M82380 PIC consists of a set of
8-bit registers to control its operations The address
map of all the registers is shown in Table 10 Since
all three register sets are identical in functions only
one set will be described
Functionally each register set can be divided into
five groups They are the four Initialization Com-
mand Words (ICW’s) the three Operation Control
Words (OCW’s) the PollInterrupt RequestIn-Serv-
ice Register the Interrupt Mask Register and the
Vector Registers A description of each group fol-
lows
62


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