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M80C186XL20 Datasheet(PDF) 17 Page - Intel Corporation |
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M80C186XL20 Datasheet(HTML) 17 Page - Intel Corporation |
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17 / 44 page  M80C186XL AC CHARACTERISTICS MAJOR CYCLE TIMINGS (READ CYCLE) TC eb55 Cto a125 C VCC e 5V g10% All timings are measured at 15V and 100 pF loading on CLKOUT unless otherwise noted All output test conditions are with CL e 50 pF For AC tests input VIL e 045V and VIH e 24V except at X1 where VIH e VCC b 05V Values Conditions Test Symbol Parameter M80C186XL16 M80C186XL20 Unit Min Max Min Max M80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once) TDVCL Data in Setup (AD) 15 10 ns TCLDX Data in Hold (AD) 3 3 ns M80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) TCHSV Status Active Delay 1 31 1 25 ns TCLSH Status Inactive Delay 1 30 1 25 ns TCLAV Address Valid Delay 1 33 1 27 ns TCLAX Address Hold 0 0 ns TCLDV Data Valid Delay 1 33 1 27 ns TCHDX Status Hold Time 10 10 ns TCHLH ALE Active Delay 20 20 ns TLHLL ALE Width TCLCL b 15 TCLCL b 15 ns TCHLL ALE Inactive Delay 20 20 ns TAVLL Address Valid to ALE Low TCLCH b 15 TCLCH b 10 ns Equal Loading TLLAX Address Hold from ALE TCHCL b 15 TCHCL b 10 ns Equal Inactive Loading TAVCH Address Valid to Clock High 0 0 ns TCLAZ Address Float Delay TCLAX 20 TCLAX 20 ns TCLCSV Chip-Select Active Delay 1 30 1 25 ns TCXCSX Chip-Select Hold from tCLCH b 10 TCLCH b 10 ns Equal Command Inactive Loading TCHCSX Chip-Select Inactive Delay 1 25 1 20 ns TDXDL DEN Inactive to DTR Low 0 0 ns Equal Loading TCVCTV Control Active Delay 1 1 31 1 22 ns TCVDEX DEN Inactive Delay 1 31 1 22 ns TCHCTV Control Active Delay 2 1 31 1 22 ns TCLLV LOCK ValidInvalid Delay 1 35 1 22 ns M80C186XL TIMING RESPONSES (Read Cycle) TAZRL Address Float to RD Active 0 0 ns TCLRL RD Active Delay 1 31 1 27 ns TRLRH RD Pulse Width 2TCLCL b 25 2TCLCL b 20 ns TCLRH RD Inactive Delay 1 31 1 27 ns TRHLH RD Inactive to ALE High TCLCH b 14 TCLCH b 14 ns Equal Loading TRHAV RD Inactive to Address TCLCL b 15 TCLCL b 15 ns Equal Active Loading 17 |
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