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87C54 Datasheet(PDF) 9 Page - Intel Corporation |
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87C54 Datasheet(HTML) 9 Page - Intel Corporation |
9 / 20 page AUTOMOTIVE 87C5487C54-20 NOTES 1 Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the VOLs of ALE and Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations In applications where capacitance loading exceeds 100 pFs the noise pulse on the ALE signal may exceed 08V In these cases it may be desirable to qualify ALE with a Schmitt Trigger or use an Address Latch with a Schmitt Trigger Strobe input 2 Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 09 VCC specification when the address lines are stabilizing 3 See Figures 6 – 9 for test conditions Minimum VCC for Power Down is 2V 4 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and 5V 5 Under steady state (non-transient) conditions IOL must be externally limited as follows Maximum IOL per port pin 10mA Maximum IOL per 8-bit port Port 0 26 mA Ports 1 2 and 3 15 mA Maximum total IOL for all output pins 71 mA If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 270849 – 7 ICC Max at other frequencies is given by Active Mode ICC Max e (125 c Osc Freq) a 8 Idle Mode ICC Max e (05 c Osc Freq) a 4 Where Osc Freq is in MHz ICC is in mA Figure 6 ICC vs Frequency 270849 – 8 All other pins disconnected TCLCH e TCHCL e 5ns Figure 7 ICC Test Condition Active Mode 270849 – 9 All other pins disconnected TCLCH e TCHCL e 5ns Figure 8 ICC Test Condition Idle Mode 270849 – 10 All other pins disconnected Figure 9 ICC Test Condition Power Down Mode VCC e 20V to 60V 270849 – 11 Figure 10 Clock Signal Waveform for ICC Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns 9 |
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