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82375SB Datasheet(PDF) 59 Page - Intel Corporation |
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82375SB Datasheet(HTML) 59 Page - Intel Corporation |
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59 / 131 page  82375EBSB a 0 – 512 KByte b 512 – 640 KByte c 640 – 768 KByte (VGA memory) d 768 – 896 KByte in eight 16 KByte sections (Expansion ROM) e 896 – 960 KByte in four 16 KByte sections (lower BIOS area) f 960 KByte to 1 MByte (upper BIOS area) g 1 MByte to the top of memory (up to 4 GByte – 2 MByte) within which a hole can be opened Accesses to the hole are not forwarded to PCI The top of the region can be programmed on 2 MByte boundaries up to 4 GByte – 2 MByte The hole can be between 64 KByte and 4 GByte – 2 MByte in 64 KByte increments and located on any 64 KByte boundary h 16 MByte – 64 KByte to 16 MByte (FF0000 – FFFFFFh) EISA memory cycles in this range are always for- warded to the PCI Bus if this range exists in main memory as defined by the MEMCS registers In this case the enabledisable control bit in EADC2 Register is a don’t care If this range is not defined in main memory (ie above the top of memory or defined as a hole in the main memory) EISA cycles to this address range are forwarded to the PCI Bus based on the enabledisable bit in the EADC2 Register (This capability is used to support access of BIOS at 16 MBytes) i 4 GByte – 2 MByte to 4 GByte The address map must be programmed in a such way that this address range is always contained within EISA This is to avoid conflict with local BIOS memory response in this address range If this region must be mapped to PCI then programming of the BIOS decoder Registers contained within the ESC must ensure that there is no conflict To map this region to PCI one of the four programmable EISA-to-PCI memory regions must be used Mapping of this region to the PCI might be required in the case when BIOS resides on the PCI and the PCIEISA system must have consistent address maps for both PCI and EISA For detailed information on the PCEB registers used to control these address regions refer to Section 31 PCEB Configuration Registers 59 |
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