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82375SB Datasheet(PDF) 12 Page - Intel Corporation |
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82375SB Datasheet(HTML) 12 Page - Intel Corporation |
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12 / 131 page  82375EBSB In addition to the main memory address decoding there are four programmable memory regions and four programmable IO regions for EISA-initiated cycles EISAISA master or DMA accesses to one of these regions are forwarded to the PCI Bus Data Buffering The PCEB contains four 16-byte wide Line Buffers for EISA-initiated cycles to the PCI Bus The Line Buffers permit prefetching of read data from PCI memory and posting of data being written to PCI memory By using burst transactions to fill or flush these buffers when appropriate the PCEB maximizes bus efficiency For example an EISA device could fill a Line Buffer with byte word or Dword transfers and the PCEB would use a PCI burst cycle to flush the filled line to PCI memory BIOS Timer The PCEB has a 16-bit BIOS Timer The timer can be used by BIOS software to implement timing loops The timer count rate is derived from the EISA clock (BCLK) and has an accuracy of g 1 ms 12 ESC Overview The PCEB and ESC form a PCI-EISA bridge The PCEBESC interface provides the inter-chip communications between these two devices The major functions provided by the ESC are described in this section EISA Controller The ESC incorporates a 32-bit master and an 8-bit slave The ESC directly drives eight EISA slots without external data or address buffering EISA system clock (BCLK) generation is integrated by dividing the PCI clock (divide by 3 or divide by 4) and wait state generation is provided The AENx and MACKx signals provide a direct interface to four EISA slots and supports eight EISA slots with encoded AENx and MACKx signals The ESC contains an 8-bit data bus (lower 8 bits of the EISA data bus) that is used to program the ESC’s internal registers Note that for transfers between the PCI and EISA Buses the PCEB provides the data path Thus the ESC does not require a full 32-bit data bus A full 32-bit address bus is provided and is used during refresh cycles and for DMA operations The ESC performs cycle translation between the EISA Bus and ISA Bus For mis-matched masterslave combinations the ESC controls the data swap buffers that are located in the PCEB This control is provided through the PCEBESC interface DMA Controller The ESC incorporates the functionality of two 82C37 DMA controllers with seven independently programma- ble channels Each channel can be programmed for 8- or 16-bit DMA device size and ISA-compatible type ‘‘A’’ type ‘‘B’’ or type ‘‘C’’ timings Full 32-bit addressing is provided The DMA controller also generates refresh cycles 12 |
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Similar Description - 82375SB |
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