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82375EB Datasheet(PDF) 27 Page - Intel Corporation |
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82375EB Datasheet(HTML) 27 Page - Intel Corporation |
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27 / 131 page  82375EBSB 30 REGISTER DESCRIPTION The PCEB contains both PCI configuration registers and IO registers The configuration registers (Table 1) are located in PCI configuration space and are only accessible from the PCI Bus The addresses shown in the table for each register are offset values that appear on AD 72 and CBE 30 The configuration registers can be accessed as Byte Word (16-bit) or Dword (32-bit) quantities All multi-byte numeric fields use ‘‘little-en- dian’’ ordering (ie lower addresses contain the least significant parts of the fields) The BIOS Timer is the only non-configuration register (Section 32 IO Registers) This register like the configuration registers is only accessible from the PCI Bus The BIOS Timer Register can be accessed as byte word or Dword quantities Some of the PCEB registers contain reserved bits These bits are labeled ‘‘Reserved’’ Software must take care to deal correctly with bit-encoded fields that are reserved On reads software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value On writes software must ensure that the values of reserved bits are preserved That is the values of reserved bit positions must first be read merged with the new values for other bit positions and the data then written back In addition to reserved bits within a register the PCEB contains address locations in the PCI configuration space that are marked ‘‘Reserved’’ (Table 1) The PCEB responds to accesses to these address locations by completing the PCI cycle When a reserved register location is read 0000h is returned Writes have no affect on the PCEB During a hard reset (PCIRST asserted) the PCEB registers are set to pre-determined default states The default values are indicated in the individual register descriptions During the address phase of a configuration cycle Bits 108 encode one of eight possible functions on a device The PCEB only supports one function that of a bridge between the PCI and EISAISA Busses This function has the code of 000 Thus for accessing PCEB configuration registers Bits 108 e000 of the ad- dress If the PCEB IDSEL is asserted and any of the above three bits is 1 the PCEB returns all zeros for a read and does not respond to a write 31 Configuration Registers Table 1 summarizes the PCEB configuration space registers Following the table is a detailed description of each register and register bit The register descriptions are arranged in the order that they appear in Table 1 The following nomenclature is used for access attributes RO Read Only If a register is read only writes to this register have no effect RW ReadWrite A register with this attribute can be read and written RWC ReadWrite Clear A register bit with this attribute can be read and written However a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect NOTE Some register fields are used to program address ranges for various PCEB functions The register contents represent the address bit value and not the signal level on the bus For example the upper address lines on the EISA Bus have inverted signals (LA 3124 ) However this inversion is auto- matically handled by the PCEB hardware and is transparent to the programmer 27 |
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