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82374SB Datasheet(PDF) 87 Page - Intel Corporation |
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82374SB Datasheet(HTML) 87 Page - Intel Corporation |
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87 / 208 page  82374EB82374SB 349 ELCREDGELEVEL CONTROL REGISTER Register Location 04D0hINT CNTRL-1 04D1hINT CNTRL-1 Default Value 00h Attribute ReadWrite Size 8 Bits The EdgeLevel Control Register is used to set the interrupts to be triggered by either the signal edge or the logic level INT0 INT1 INT2 INT8 INT13 must be set to edge sensitive After a reset all the INT signals are set to edge sensitive Programming Considerations If an interrupt is switched from level to edge sensitive a false interrupt is generated on that interrupt line If the IRQx line is high then switching the leveledge bet from a 1 to a 0 causes the interrupt controller to detect an interrupt Also note that even if this interrupt is masked when programming this register the interrupt controller still latches the false interrupt As soon as this interrupt is unmasked the false interrupt is processed Thus before switching the edgelevel function disable interrupts to the processor (either mask interrupts or CLI instruction) Then program the ELCR Register Finally re-initialize the interrupt controller to clear the false interrupt Bit Description 70 EdgeLevel Select The bits select if the interrupts are triggered by either the signal edge or the logic level A 0 bit represents an edge sensitive interrupt anda1isfor level sensitive Bit 20 and bit 13 must be set to 0 After A reset or power-on these registers are set to 00h Bit Port 04D0h Port 04D1h 0 INT0 INT8 1 INT1 INT9 2 INT2 INT10 3 INT3 INT11 4 INT4 INT12 5 INT5 INT13 6 INT6 INT14 7 INT7 INT15 3410 NMISCNMI STATUS AND CONTROL REGISTER Register Location 061h Default Value X0X0 0000 Attribute ReadWrite Read Only Size 8 Bits This register is used to check the status of different system components control the output of the Speaker Counter (Timer 1 Counter 2) and gate the counter output that drives the SPKR signal This register also controls NMI generation and reports NMI source status Note that NMI generation is globally enableddisabled via the NMIERTC Register and NMI generation for SERR is controlled via the MS Register Bits 74 of this register are read-only and must be written as 0s when writing to this register Bits 30 are readwrite Follow- ing reset bit 7 returns the PCI System Board Parity Error status (PERR ) and bit 5 is undetermined until Counter 2 is properly programmed 87 |
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