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82371SB Datasheet(PDF) 71 Page - Intel Corporation |
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82371SB Datasheet(HTML) 71 Page - Intel Corporation |
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71 / 122 page  E 82371FB (PIIX) AND 82371SB (PIIX3) 71 2.5.3.3. ICW3—Initialization Command Word 3 Register I/O Address: INT CNTRL-1—021h Default Value: All bits undefined Attribute: Write Only The meaning of ICW3 differs between CNTRL-1 and CNTRL-2. On CNTRL-1, the master controller, ICW3 indicates which CNTRL-1 IRQ line physically connects the INTR output of CNTRL-2 to CNTRL-1. Bit Description 7:3 Reserved. Must be programmed to all 0s. 2 Cascaded Mode Enable. This bit must be programmed to 1 selecting cascade mode. 1:0 Reserved. Must be programmed to all 0s. 2.5.3.4. ICW3—Initialization Command Word 3 Register I/O Address: INT CNTRL-2—0A1h Default Value: All bits undefined Attribute: Write Only On CNTRL-2 (the slave controller), ICW3 is the slave identification code broadcast by CNTRL-1. Bit Description 7:3 Reserved. Must be programmed to all 0s. 2:0 Slave Identification Code. Must be programmed to 010b. 2.5.3.5. ICW4—Initialization Command Word 4 Register I/O Address: INT CNTRL-1—021h; INT CNTRL-2—0A1h Default Value: 01h Attribute: Write Only Both PIIX/PIIX3 interrupt controllers must have ICW4 programmed as part of their initialization sequence. Bit Description 7:5 Reserved. Must be programmed to all 0s. 4 Special Fully Nested Mode (SFNM). Bit 4, SFNM, should normally be disabled by writing a 0 to this bit. If SFNM=1, the special fully nested mode is programmed. 3 Buffered mode (BUF). Must be programmed to 0 selecting non-buffered mode. 2 Master/Slave in Buffered Mode. Should always be programmed to 0. Bit not used. 1 AEOI (Automatic End of Interrupt). This bit should normally be programmed to 0. This is the normal end of interrupt. If this bit is 1, the automatic end of interrupt mode is programmed. 0 Microprocessor Mode. Must be programmed to 1 indicating an Intel Architecture-based system. |
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