 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
82371SB Datasheet(PDF) 49 Page - Intel Corporation |
|
||||||||||||||||||||||||||||||
82371SB Datasheet(HTML) 49 Page - Intel Corporation |
|
|
49 / 122 page  E 82371FB (PIIX) AND 82371SB (PIIX3) 49 Bit Description 8 Data Parity Detected (DPD). (Not Implemented) Read as 0. 7 Fast Back to back Capable (FBC)—RO. Hardwired to 1. This bit indicates to the PCI Master that PIIX, as a target, is capable of accepting fast back-to-back transactions. 6:0 Reserved. Read as 0’s. 2.3.5. RID—REVISION IDENTIFICATION REGISTER (Function 1) Address Offset: 08h Default Value: Refer to applicable specification update document Attribute: Read Only This 8 bit register contains device stepping information. Writes to this register have no effect. Bit Description 7:0 Revision ID Byte. The register is hardwired to the default value during manufacturing. 2.3.6. CLASSC CLASS CODE REGISTER (Function 1) Address Offset: 09 −0Bh Default Value: 010180h Attribute: Read Only This register contains the device programming interface information related to the Sub-Class Code and Base Class Code definition for the PIIX3 (function 1). This register also identifies the Base Class Code and the function sub-class in relation to the Base Class Code. Bit Description 23:1 6 Base Class Code (BASEC). 01h=Mass storage device. 15:8 Sub-Class Code (SCC). 01h=IDE controller. 7:0 Programming Interface (PI). 80h=Capable of IDE bus master operation. 2.3.7. MLT—MASTER LATENCY TIMER REGISTER (Function 1) Address Offset: 0Dh Default Value: 00h Attribute: Read / Write MLT controls the amount of time PIIX, as a bus master, can burst data on the PCI Bus. The count value is an 8-bit quantity. However, MLT[3:0] are reserved and 0 when determining the count value. MLT is cleared and suspended when PIIX/PIIX3 is not asserting FRAME#. When PIIX/PIIX3 asserts FRAME#, the counter begins counting. If the PIIX/PIIX3 finishes its transaction before the count expires, the MLT count is ignored. If the count expires before the transaction completes (count = # of clocks programmed in MLT), PIIX/PIIX3 initiates a transaction termination as soon as its PHLDA# is removed. The number of clocks programmed in the MLT represents the guaranteed time slice (measured in PCI clocks) allotted to PIIX. The default value of MLT is 00h or 0 PCI clocks. |
Similar Part No. - 82371SB |
|
Similar Description - 82371SB |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
