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FW82371 Datasheet(PDF) 8 Page - Intel Corporation |
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FW82371 Datasheet(HTML) 8 Page - Intel Corporation |
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8 / 284 page  82371AB (PIIX4) 8 4/9/97 2:23 PM PIIX4aDS INTEL CONFIDENTIAL (until publication date) PRELIMINARY 7.1.23. DEVRESH—Device Resource H (Function 3)................................................................................133 7.1.24. DEVRESI—Device Resource I (Function 3) ...................................................................................133 7.1.25. DEVRESJ Device Resource J (Function 3) .................................................................................134 7.1.26. PMREGMISC Miscellaneous Power Management (Function 3) ..................................................134 7.1.27. SMBBA—SMBUS Base Address (Function 3)................................................................................135 7.1.28. SMBHSTCFG SMBUS Host Configuration (Function 3) ..............................................................135 7.1.29. SMBSLVC SMBUS Slave Command (Function 3).......................................................................135 7.1.30. SMBSHDW1 SMBUS Slave Shadow Port 1 (Function 3) ............................................................136 7.1.31. SMBSHDW2 SMBUS Slave Shadow Port 2 (Function 3) ............................................................136 7.1.32. SMBREV SMBUS Revision Identification (Function 3) ................................................................136 7.2. Power Management IO Space Registers .................................................................................................137 7.2.1. PMSTS Power Management Status Register (IO) .........................................................................137 7.2.2. PMEN Power Management Resume Enable Register (IO)............................................................138 7.2.3. PMCNTRL Power Management Control Register (IO)...................................................................138 7.2.4. PMTMR Power Management Timer Register (IO)..........................................................................139 7.2.5. GPSTS General Purpose Status Register (IO) ..............................................................................139 7.2.6. GPEN General Purpose Enable Register (IO) ...............................................................................140 7.2.7. PCNTRL Processor Control Register (IO)......................................................................................141 7.2.8. PLVL2 Processor Level 2 Register (IO) .........................................................................................142 7.2.9. PLVL3 Processor Level 3 Register (IO) ........................................................................................142 7.2.10. GLBSTS Global Status Register (IO) ...........................................................................................143 7.2.11. DEVSTS Device Status Register (IO) ..........................................................................................144 7.2.12. GLBEN Global Enable Register (IO) ............................................................................................144 7.2.13. GLBCTL Global Control Register (IO) ..........................................................................................145 7.2.14. DEVCTL Device Control Register (IO) .........................................................................................146 7.2.15. GPIREG General Purpose Input Register (IO).............................................................................147 7.2.16. GPOREG General Purpose Output Register (IO)........................................................................148 7.3. SMBus IO Space Registers......................................................................................................................148 7.3.1. SMBHSTSTS SMBus Host Status Register (IO)............................................................................148 7.3.2. SMBSLVSTS SMBus Slave Status Register (IO) ..........................................................................149 7.3.3. SMBHSTCNT SMBus Host Control Register (IO)..........................................................................150 7.3.4. SMBHSTCMD SMBus Host Command Register (IO)....................................................................150 7.3.5. SMBHSTADD SMBus Host Address Register (IO)........................................................................151 7.3.6. SMBHSTDAT0 SMBus Host Data 0 Register (IO).........................................................................151 7.3.7. SMBHSTDAT1 SMBus Host Data 1 Register (IO).........................................................................151 7.3.8. SMBBLKDAT SMBus Block Data Register (IO).............................................................................152 7.3.9. SMBSLVCNT SMBus Slave Control Register (IO).........................................................................152 7.3.10. SMBSHDWCMD SMBus Shadow Command Register (IO).........................................................153 7.3.11. SMBSLVEVT SMBus Slave Event Register (IO) .........................................................................153 7.3.12. SMBSLVDAT SMBus Slave Data Register (IO)...........................................................................153 8.0. PCI/ISA BRIDGE FUNCTIONAL DESCRIPTION ......................................................................................154 8.1. Memory and IO Address Map...................................................................................................................154 |
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Similar Description - FW82371 |
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