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82371AB Datasheet(PDF) 91 Page - Intel Corporation |
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82371AB Datasheet(HTML) 91 Page - Intel Corporation |
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91 / 284 page  82371AB (PIIX4) 91 4/9/97 2:23 PM PIIX4aDS INTEL CONFIDENTIAL (until publication date) PRELIMINARY 5.1.5. RID—REVISION IDENTIFICATION REGISTER (FUNCTION 1) Address Offset: 08h Default Value: Initial Stepping=00h. Refer to PIIX4 Specification Updates for other values programmed here. Attribute: Read Only This 8-bit register contains device stepping information. Writes to this register have no effect. Bit Description 7:0 Revision ID Byte. The register is hardwired to the default value. 5.1.6. CLASSC—CLASS CODE REGISTER (FUNCTION 1) Address Offset: 09 −0Bh Default Value: 010180h Attribute: Read Only This register identifies the Base Class Code, Sub Class Code, and Device Programming interface for PIIX4 PCI function 1. Bit Description 23:16 Base Class Code (BASEC). 01h=Mass storage device. 15:8 Sub Class Code (SCC). 01h=IDE controller. 7:0 Programming Interface (PI). 80h=Capable of IDE bus master operation. 5.1.7. MLT—MASTER LATENCY TIMER REGISTER (FUNCTION 1) Address Offset: 0Dh Default Value: 00h Attribute: Read/Write MLT controls the amount of time PIIX4, as a bus master, can burst data on the PCI Bus. The count value is an 8- bit quantity. However, MLT[3:0] are reserved and 0 when determining the count value. The Master Latency Timer is cleared and suspended when PIIX4 is not asserting FRAME#. When PIIX4 asserts FRAME#, the counter begins counting. If PIIX4 finishes its transaction before the count expires, the MLT count is ignored. If the count expires before the transaction completes (count=# of clocks programmed in MLT), PIIX4 initiates a transaction termination as soon as its PHLDA# is removed. The number of clocks programmed in the MLT represents the guaranteed time slice (measured in PCI clocks) allotted to PIIX4. Bit Description 7:4 Master Latency Timer Count Value (MLTC). PIIX4-initiated PCI burst cycles can last indefinitely, as long as PHLDA# remains active. However, if PHLDA# is negated after the burst cycle is initiated, PIIX4 limits the burst cycle to the number of PCI Bus clocks specified by this field. 3:0 Reserved. |
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