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RC28F320C3 Datasheet(PDF) 9 Page - Intel Corporation |
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RC28F320C3 Datasheet(HTML) 9 Page - Intel Corporation |
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9 / 59 page  E 3 VOLT ADVANCED+ BOOT BLOCK 9 PRODUCT PREVIEW Table 2. 3 Volt Advanced+ Boot Block Pin Descriptions Symbol Type Name and Function A0–A21 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. 8-Mbit x 8 A[0-19], 16-Mbit x 8 A[0-20], 32-Mbit x 8 A[0-21] 8-Mbit x 16 A[0-18], 16-Mbit x 16 A[0-19], 32-Mbit x 16 A[0-20] DQ0–DQ7 INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. Outputs array, configuration and status register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. DQ8–DQ15 INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. Outputs array and configuration data. The data pins float to tri-state when the chip is de-selected. Not included on x8 products. CE# INPUT CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a read operation. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse. RP# INPUT RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep power-down mode. When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD). When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. WP# INPUT WRITE PROTECT: Controls the lock-down function of the flexible Locking feature When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. When WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are now locked and can be unlocked and locked through software. After WP# goes low, any blocks previously marked lock-down revert to that state. See Section 3.3 for details on block locking. VCC SUPPLY DEVICE POWER SUPPLY: [2.7 V–3.6 V] Supplies power for device operations. |
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