80960CA-25 datasheet(6/62 Pages) INTEL

Part #	80960CA-25

Description	SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

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Manufacturer	INTEL [Intel Corporation]

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SPECIAL ENVIRONMENT 80960CA-25 -16

21 The C-Series Core

The C-Series core is a very high performance micro-

architectural implementation of the 80960 Core Ar-

chitecture The C-Series core can sustain execution

of two instructions per clock (50 MIPs at 25 MHz)

To achieve this level of performance Intel has incor-

porated state-of-the-art silicon technology and inno-

vative microarchitectural constructs into the imple-

mentation of the C-Series core Factors that contrib-

ute to the core’s performance include

Parallel instruction decoding allows issuance of

up to three instructions per clock

Single-clock execution of most instructions

Parallel instruction decode allows sustained

simultaneous execution of two single-clock in-

structions every clock cycle

Efficient instruction pipeline minimizes pipeline

break losses

Register and resource scoreboarding allow simul-

taneous multi-clock instruction execution

Branch look-ahead and prediction allows many

branches to execute with no pipeline break

Local Register Cache integrated on-chip caches

CallReturn context

Two-way set associative 1 Kbyte integrated in-

struction cache

1 Kbyte integrated Data RAM sustains a four-

word (128-bit) access every clock cycle

22 Pipelined Burst Bus

A 32-bit high performance bus controller interfaces

the 80960CA to external memory and peripherals

The Bus Control Unit features a maximum transfer

rate of 100 Mbytes per second (at 25 MHz) Internal-

ly programmable wait states and 16 separately con-

figurable memory regions allow the processor to in-

terface with a variety of memory subsystems with a

minimum of system complexity and a maximum of

performance The Bus Controller’s main features in-

clude

Demultiplexed Burst Bus to exploit most efficient

DRAM access modes

Address Pipelining to reduce memory cost while

maintaining performance

32- 16- and 8-bit modes for IO interfacing ease

Full internal wait state generation to reduce sys-

tem cost

Little and Big Endian support to ease application

development

Unaligned access support for code portability

Three-deep request queue to decouple the bus

from the core

23 Flexible DMA Controller

A four-channel DMA controller provides high speed

DMA control for data transfers involving peripherals

and memory The DMA provides advanced features

such as data chaining byte assembly and disassem-

bly and a high performance fly-by mode capable of

transfer speeds of up to 45 Mbytes per second at

25 MHz The DMA controller features a performance

and flexibility which is only possible by integrating

the DMA controller and the 80960CA core

24 Priority interrupt Controller

A programmable-priority interrupt controller man-

ages up to 248 external sources through the 8-bit

external interrupt port The interrupt Unit also han-

dles the four internal sources from the DMA control-

ler and a single non-maskable interrupt input The

8-bit interrupt port can also be configured to provide

individual interrupt sources that are level or edge

triggered

Interrupts in the 80960CA are prioritized and sig-

naled within 270 ns of the request If the interrupt is

of higher priority than the processor priority the con-

text switch to the interrupt routine typically is com-

plete in another 480 ns The interrupt unit provides

the mechanism for the low latency and high through-

put interrupt service which is essential for embedded

applications

6

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