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80960CA-25 Datasheet(PDF) 3 Page - Intel Corporation

Part No. 80960CA-25
Description  SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
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Maker  INTEL [Intel Corporation]
Homepage  http://www.intel.com
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80960CA-25 Datasheet(HTML) 3 Page - Intel Corporation

 
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CONTENTS
PAGE
LIST OF FIGURES
Figure 1
80960CA Block Diagram
5
Figure 2
80960CA PGA PinoutView from Top (Pins Facing Down)
17
Figure 3
80960CA PGA PinoutView from Bottom (Pins Facing Up)
18
Figure 4
Measuring 80960CA PGA Case Temperature
19
Figure 5
Register g0
21
Figure 6
AC Test Load
28
Figure 7
Input and Output Clocks Waveform
28
Figure 8
CLKIN Waveform
28
Figure 9
Output Delay and Float Waveform
29
Figure 10 Input Setup and Hold Waveform
29
Figure 11 NMI XINT70 Input Setup and Hold Waveform
30
Figure 12 Hold Acknowledge Timings
30
Figure 13 Bus Backoff (BOFF) Timings
31
Figure 14 Relative Timings Waveforms
32
Figure 15 Output Delay or Hold vs Load Capacitance
32
Figure 16 Rise and Fall Time Derating at Highest Operating Temperature
and Minimum VCC
33
Figure 17 ICC vs Frequency and Temperature
33
Figure 18 Cold Reset Waveform
35
Figure 19 Warm Reset Waveform
36
Figure 20 Entering the ONCE State
37
Figure 21 Clock Synchronization in the 2-x Clock Mode
38
Figure 22 Clock Synchronization in the 1-x Clock Mode
38
Figure 23 Non-Burst Non-Pipelined Requests without Wait States
39
Figure 24 Non-Burst Non-Pipelined Read Request with Wait States
40
Figure 25 Non-Burst Non-Pipelined Write Request with Wait States
41
Figure 26 Burst Non-Pipelined Read Request without Wait States 32-Bit Bus
42
Figure 27 Burst Non-Pipelined Read Request with Wait States 32-Bit Bus
43
Figure 28 Burst Non-Pipelined Write Request without Wait States 32-Bit Bus
44
Figure 29 Burst Non-Pipelined Write Request with Wait States 32-Bit Bus
45
Figure 30 Burst Non-Pipelined Read Request with Wait States 16-Bit Bus
46
Figure 31 Burst Non-Pipelined Read Request with Wait States 8-Bit Bus
47
Figure 32 Non-Burst Pipelined Read Request without Wait States 32-Bit Bus
48
Figure 33 Non-Burst Pipelined Read Request with Wait States 32-Bit Bus
49
Figure 34 Burst Pipelined Read Request without Wait States 32-Bit Bus
50
Figure 35 Burst Pipelined Read Request with Wait States 32-Bit Bus
51
Figure 36 Burst Pipelined Read Request with Wait States 16-Bit Bus
52
Figure 37 Burst Pipelined Read Request with Wait States 8-Bit Bus
53
3


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