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80296SA Datasheet(PDF) 11 Page - Intel Corporation |
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80296SA Datasheet(HTML) 11 Page - Intel Corporation |
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11 / 40 page  PRELIMINARY 7 80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER BREQ# O Bus Request This active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. When the bus-hold protocol is enabled (WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bus- hold protocol is disabled (WSR.7 is cleared). The microcontroller can assert BREQ# at the same time as or after it asserts HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted. BREQ# shares a package pin with P2.3. CLKOUT O Clock Output Output of the internal clock generator. The CLKOUT frequency is ½ the internal operating frequency (f). CLKOUT has a 50% duty cycle. CLKOUT shares a package pin with P2.7. CS5:0# O Chip-select Lines 0–5 The active-low output CS x# is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x or chip select x+1 if remapping is enabled. If the external memory address is outside the range assigned to the six chip selects, no chip-select output is asserted and the bus configuration defaults to the CS5# values. Immediately following reset, CS0# is automatically assigned to the range FF2000– FF20FFH. CS5:0# share package pins with P3.5:0. EPA3:0 I/O Event Processor Array (EPA) Capture/Compare Channels High-speed input/output signals for the EPA capture/compare channels. For high- speed PWM applications, the outputs of two EPA channels (either EPA0 and EPA1 or EPA2 and EPA3) can be remapped to produce a PWM waveform on a shared output pin. EPA3:0 share package pins with P1.3:0. EPORT.3:0 I/O Extended Addressing Port This is a standard 4-bit, bidirectional port. EPORT.3:0 share package pins with A19:16. Table 4. Signal Descriptions (Continued) Name Type Description |
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