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376 Datasheet(PDF) 16 Page - Intel Corporation |
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376 Datasheet(HTML) 16 Page - Intel Corporation |
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16 / 95 page  376 EMBEDDED PROCESSOR 26 IO Space The 80376 has two distinct physical address spaces physical memory and IO Generally pe- ripherals are placed in IO space although the 80376 also supports memory-mapped peripherals The IO space consists of 64 Kbytes which can be divided into 64K 8-bit ports 32K 16-bit ports or any combination of ports which add to no more than 64 Kbytes The MIO pin acts as an additional address line thus allowing the system designer to easily de- termine which address space the processor is ac- cessing Note that the IO address refers to a physi- cal address The IO ports are accessed by the IN and OUT in- structions with the port address supplied as an im- mediate 8-bit constant in the instruction or in the DX register All 8-bit and 16-bit port addresses are zero extended on the upper address lines The IO in- structions cause the MIO pin to be driven LOW IO port addresses 00F8H through 00FFH are reserved for use by Intel 27 Interrupts and Exceptions Interrupts and exceptions alter the normal program flow in order to handle external events report errors or exceptional conditons The difference between in- terrupts and exceptions is that interrupts are used to handle asynchronous external events while excep- tions handle instruction faults Although a program can generate a software interrupt via an INT N in- struction the processor treats software interrupts as exceptions Hardware interrupts occur as the result of an exter- nal event and are classified into two types maskable or non-maskable Interrupts are serviced after the execution of the current instruction After the inter- rupt handler is finished servicing the interrupt exe- cution proceeds with the instruction immediately af- ter the interrupted instruction Exceptions are classified as faults traps or aborts depending on the way they are reported and wheth- er or not restart of the instruction causing the excep- tion is suported Faults are exceptions that are de- tected and serviced before the execution of the faulting instruction Traps are exceptions that are reported immediately after the execution of the in- struction which caused the problem Aborts are ex- ceptions which do not permit the precise location of the instruction causing the exception to be deter- mined Thus when an interrupt service routine has been completed execution proceeds from the in- struction immediately following the interrupted in- struction On the other hand the return address from an exceptionfault routine will always point at the instruction causing the exception and include any leading instruction prefixes Table 25 summarizes the possible interrupts for the 80376 and shows where the return address points to The 80376 has the ability to handle up to 256 differ- ent interruptsexceptions In order to service the in- terrupts a table with up to 256 interrupt vectors must be defined The interrupt vectors are simply pointers to the appropriate interrupt service routine The interrupt vectors are 8-byte quantities which are put in an Interrupt Descriptor Table Of the 256 pos- sible interrupts 32 are reserved for use by Intel and the remaining 224 are free to be used by the system designer INTERRUPT PROCESSING When an interrupt occurs the following actions hap- pen First the current program address and the Flags are saved on the stack to allow resumption of the interrupted program Next an 8-bit vector is sup- plied to the 80376 which identifies the appropriate entry in the interrupt table The table contains either an Interrupt Gate a Trap Gate or a Task Gate that will point to an interrupt procedure or task The user supplied interrupt service routine is executed Final- ly when an IRET instruction is executed the old processor state is restored and program execution resumes at the appropriate instruction The 8-bit interrupt vector is supplied to the 80376 in several different ways exceptions supply the inter- rupt vector internally software INT instructions con- tain or imply the vector maskable hardware inter- rupts supply the 8-bit vector via the interrupt ac- knowledge bus sequence Non-Maskable hardware interrupts are assigned to interrupt vector 2 Maskable Interrupt Maskable interrupts are the most common way to respond to asynchronous external hardware events A hardware interrupt occurs when the INTR is pulled HIGH and the Interrupt Flag bit (IF) is enabled The processor only responds to interrupts between in- structions (string instructions have an ‘‘interrupt win- dow’’ between memory moves which allows inter- rupts during long string moves) When an interrupt occurs the processor reads an 8-bit vector supplied by the hardware which identifies the source of the interrupt (one of 224 user defined interrupts) 16 |
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