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P28F020-150 Datasheet(PDF) 8 Page - Intel Corporation |
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P28F020-150 Datasheet(HTML) 8 Page - Intel Corporation |
8 / 38 page 28F020 E 8 28F020 28F020 A 0-A17 DQ 0-DQ7 CE# WE# OE# A 0-A17 DQ 0 -DQ7 CE# BHE# OE# V CC V CC V PP V PP 80C186 System Bus A 1-A18 DQ 8 -DQ15 Address Decoded Chip Select DQ 0-DQ7 WE# WR# RD# V CC V CC A 0 0245_03 Figure 3. 28F020 in an 80C186 System 2.0 PRINCIPLES OF OPERATION Flash memory augments EPROM functionality with in-circuit electrical erasure and reprogramming. The 28F020 introduces a command register to manage this new functionality. The command register allows for 100% TTL-level control inputs, fixed power supplies during erasure and programming, and maximum EPROM compatibility. In the absence of high voltage on the VPP pin, the 28F020 is a read-only memory. Manipulation of the external memory control pins yields the standard EPROM read, standby, output disable, and intelligent identifier operations. The same EPROM read, standby, and output disable operations are available when high voltage is applied to the VPP pin. In addition, high voltage on VPP enables erasure and programming of the device. All functions associated with altering memory contents—intelligent identifier, erase, erase verify, program, and program verify—are accessed via the command register. Commands are written to the register using standard microprocessor write timings. Register contents serve as input to an internal state machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for programming or erase operations. With the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or output data for erase and program verification. 2.1 Integrated Stop Timer Successive command write cycles define the durations of program and erase operations; specifically, the program or erase time durations are normally terminated by associated Program or Erase Verify commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate Verify or Reset command. |
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