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PA28F400BX-T60 Datasheet(PDF) 9 Page - Intel Corporation |
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PA28F400BX-T60 Datasheet(HTML) 9 Page - Intel Corporation |
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9 / 50 page  28F400BX-TB 28F004BX-TB 15 28F400BX Pin Descriptions Symbol Type Name and Function A0–A17 I ADDRESS INPUTS for memory addresses Addresses are internally latched during a write cycle A9 I ADDRESS INPUT When A9 is at 12V the signature mode is accessed During this mode A0 decodes between the manufacturer and device ID’s When BYTE is at a logic low only the lower byte of the signatures are read DQ15 Ab1 is a don’t care in the signature mode when BYTE is low DQ0–DQ7 IO DATA INPUTSOUTPUTS Inputs array data on the second CE and WE cycle during a program command Inputs commands to the command user interface when CE and WE are active Data is internally latched during the write and program cycles Outputs array Intelligent Identifier and Status Register data The data pins float to tri-state when the chip is deselected or the outputs are disabled DQ8–DQ15 IO DATA INPUTSOUTPUTS Inputs array data on the second CE and WE cycle during a program command Data is internally latched during the write and program cycles Outputs array data The data pins float to tri-state when the chip is deselected or the outputs are disabled as in the byte-wide mode (BYTE e ‘‘0’’) In the byte-wide mode DQ15 Ab1 becomes the lowest order address for data output on DQ0-DQ7 CE I CHIP ENABLE Activates the device’s control logic input buffers decoders and sense amplifiers CE is active low CE high deselects the memory device and reduces power consumption to standby levels If CE and RP are high but not at a CMOS high level the standby current will increase due to current flow through the CE and RP input stages RP I RESETDEEP POWER-DOWN Provides three-state control Puts the device in deep power- down mode Locks the boot block from programerase When RP is at logic high level and equals 65V maximum the boot block is locked and cannot be programmed or erased When RP e 114V minimum the boot block is unlocked and can be programmed or erased When RP is at a logic low level the boot block is locked the deep power-down mode is enabled and the WSM is reset preventing any blocks from being programmed or erased therefore providing data protection during power transitions When RP transitions from logic low to logic high the flash memory enters the read-array mode OE I OUTPUT ENABLE Gates the device’s outputs through the data buffers during a read cycle OE is active low WE I WRITE ENABLE Controls writes to the Command Register and array blocks WE is active low Addresses and data are latched on the rising edge of the WE pulse BYTE I BYTE ENABLE Controls whether the device operates in the byte-wide mode (x8) or the word-wide mode (x16) BYTE pin must be controlled at CMOS levels to meet 100A CMOS current in the standby mode BYTE e ‘‘0’’ enables the byte-wide mode where data is read and programmed on DQ0–DQ7 and DQ15 Ab1 becomes the lowest order address that decodes between the upper and lower byte DQ8–DQ14 are tri-stated during the byte-wide mode BYTE e ‘‘1’’ enables the word-wide mode where data is read and programmed on DQ0–DQ15 VPP PROGRAMERASE POWER SUPPLY For erasing memory array blocks or programming data in each block Note VPP k VPPLMAX memory contents cannot be altered VCC DEVICE POWER SUPPLY (5V g10% 5V g5%) GND GROUND For all internal circuitry NC NO CONNECT Pin may be driven or left floating DU DON’T USE PIN Pin should not be connected to anything 9 |
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