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AD5100 Datasheet(PDF) 26 Page - Analog Devices

Part No. AD5100
Description  System Management IC with Factory Programmed Quad Voltage Monitoring and Supervisory Functions
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5100 Datasheet(HTML) 26 Page - Analog Devices

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AD5100
Rev. A | Page 26 of 36
I2C SERIAL INTERFACE
Control of the AD5100 is via an I2C-compatible serial bus. The
AD5100 is connected to this bus as a slave device (the AD5100
has no master capabilities).
The 2-wire serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a start
condition, which occurs when SDA goes from high to low
while SCL is high. The following byte is the slave address
byte, which consists of the 7-bit slave address followed by
an R/W bit that determines whether data is read from or
written to the slave device
2.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL.
3.
When all data bits have been read or written, a stop
condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a stop condi-
tion. In the read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains
high). The master then brings the SDA line low before the
10th clock pulse and high during the 10th clock pulse to
establish a stop condition.
For the AD5100, write operations contain either one or two
bytes, while read operations contain one byte. The AD5100
makes use of an address pointer register. This address pointer
sets up one of the other registers for the second byte of the write
operation or for a subsequent read operation. Table 12 shows
the structure of the address pointer register. Bits [6:0] signify
the address of the register that is to be written to or read from.
Bit 7 is a reserved bit and should be 0 for normal write/read
operations.
Table 12. Address Pointer Register Structure
Bit Number
Function
7
Reserved
6
Address Bit 6
5
Address Bit 5
4
Address Bit 4
3
Address Bit 3
2
Address Bit 2
1
Address Bit 1
0
Address Bit 0 (LSB)
SCL
The serial input register clock pin shifts in one bit at a time
on positive clock edges. An external 2.2 kΩ to 10 kΩ pull-up
resistor is needed. The pull-up resistor should be tied to V3MON,
provided V3MON is sub-5 V.
SDA
The serial data input/output pin shifts in one bit at a time on
positive clock edges, with the MSB loaded first. An external
2.2 kΩ to 10 kΩ pull-up resistor is needed. The pull-up resistor
should be tied to V3MON , provided V3MON is sub-5 V.
AD0
The AD5100 has a 7-bit slave address. The six MSBs are 010111,
and the LSB is determined by the state of the AD0 pin. When the
I2C slave address pin, AD0, is low, the 7-bit AD5100 slave address
is 0101110. When AD0 is high, the 7-bit AD5100 slave address
is 0101111 (pulled up to 3.3 V maximum).
The AD0 pin allows the user to connect two AD5100 devices
to the same I2C bus . Table 13 and Figure 20 show an example
of two AD5100 devices operating on the same serial bus
independently.
Table 13. Slave Address Decoding Scheme
AD0 Programming Bit
AD0 Device Pin
Device Addressed
0
0 V
0x2E (U1)
1
3.3 V max
0x2F (U2)
SCL
SDA
5V
Rp
Rp
SDA
AD0
SCL
AD5100
U2
5V
SDA
AD0
SCL
AD5100
U1
MASTER
3.3V MAX
Figure 20. Two AD5100 Devices on One Bus


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