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DT28F160S3-100 Datasheet(PDF) 7 Page - Intel Corporation

Part # DT28F160S3-100
Description  WORD-WIDE FlashFile MEMORY FAMILY
Download  52 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

DT28F160S3-100 Datasheet(HTML) 7 Page - Intel Corporation

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E
28F160S3, 28F320S3
7
ADVANCE INFORMATION
Table 1. Pin Descriptions
Sym
Type
Name and Function
A0–A21
INPUT
ADDRESS INPUTS: Address inputs for read and write operations are internally
latched during a write cycle. A0 selects high or low byte when operating in x8 mode.
In x16 mode, A0 is not used; input buffer is off.
16-Mbit
→ A
0–A20
32-Mbit
→ A
0–A21
DQ0
DQ15
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI write cycles;
outputs data during memory array, Status Register, query and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or outputs
are disabled. Data is internally latched during a write cycle.
CE0#,
CE1#
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. With CE0# or CE1# high, the device is deselected and power
consumption reduces to standby levels. Both CE0# and CE1# must be low to select
the device. Device selection occurs with the latter falling edge of CE0# or CE1#. The
first rising edge of CE0# or CE1# disables the device.
RP#
INPUT
RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during system power transitions, puts the device in
deep power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
OE#
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE#
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
STS
OPEN
DRAIN
OUTPUT
STATUS: Indicates the status of the internal state machine. When configured in
level mode (default), it acts as a RY/BY# pin. For this and alternate configurations
of the STATUS pin, see the Configuration command. Tie STS to VCC with a pull-up
resistor.
WP#
INPUT
WRITE PROTECT: Master control for block locking. When VIL, locked blocks
cannot be erased or programmed, and block lock-bits cannot be set or cleared.
BYTE#
INPUT
BYTE ENABLE: Configures x8 mode (low) or x16 mode (high).
VPP
SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
Necessary voltage to perform block erase, program, and lock-bit configuration
operations. Do not float any power pins.
VCC
SUPPLY DEVICE POWER SUPPLY: Do not float any power pins. Do not attempt block
erase, program, or block-lock configuration with invalid VCC values.
GND
SUPPLY GROUND: Do not float any ground pins.
NC
NO CONNECT: Lead is not internally connected; it may be driven or floated.


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