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28F016XS Datasheet(PDF) 19 Page - Intel Corporation |
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28F016XS Datasheet(HTML) 19 Page - Intel Corporation |
19 / 54 page E 28F016XS FLASH MEMORY 19 4/15/97 9:41 AM 9053204.DOC INTEL CONFIDENTIAL (until publication date) 4.4 28F016XS—Enhanced Command Bus Definitions First Bus Cycle Second Bus Cycle Command Notes Oper Addr Data (4) Oper Addr Data (4) Read Extended Status Register 1 Write X xx71H Read RA GSRD BSRD Lock Block/Confirm Write X xx77H Write BA xxD0H Upload Status Bits/Confirm 2 Write X xx97H Write X xxD0H Device Configuration 3 Write X xx96H Write X DCCD ADDRESS DATA BA = Block Address AD = Array Data RA = Extended Register Address BSRD = BSR Data PA = Program Address GSRD = GSR Data X = Don’t Care DCCD = Device Configuration Code Data NOTES: 1. RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register memory maps. 2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit status. 3. This command sets the SFI Configuration allowing the device to be optimized for the specific sytem operating frequency. 4. The upper byte of the Data bus (D8–15) during command writes is a “Don’t Care” in x16 operation of the device. |
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