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IA2910A

Microprogram Controller

Copyright

© 1999, InnovASIC Inc.

Customer Specific IC Solutions

Instruction 8 RFCT is the REPEAT LOOP, COUNTER NOT EQUAL ZERO instruction.

This microinstruction makes use of the decrementing capability of the register/counter. To be

useful, some previous instruction, such as 4, must have loaded a count value into the

register/counter. This instruction checks to see whether the register/counter contains a non-zero

value. If so, the register/counter is decremented, and the address of the next microinstruction is

taken from the top of the stack. If the register counter contains zero, the loop exit condition is

occurring; control falls through to the next sequential microinstruction by selecting uPC; the stack

is POP’d by decrementing the stack pointer, but the contents of the top of the stack are thrown

away.

An example of the RFCT instruction is shown in Figure II. In this example, location 50 most likely

would contain a PUSH/CONDITIONAL LOAD COUNTER instruction which would have

caused address 51 to be PUSHed on the stack and the counter to be loaded with the proper value

for looping the desired number of times.

In this example, since the loop test is made at the end of the instructions to be repeated

(microaddress 54), the proper value to be loaded by the instructions at address 50 is one less than

the desired number of passes through the loop. This method allows a loop to be executed 1 to

4096 times. If it is desired to execute the loop from 0 to 4095 times, the firmware should be

written to make the loop exit test immediately after loop entry.

Instruction 9 RPCT is the REPEAT PIPELINE REGISTER, COUNTER NOT EQUAL

ZERO instruction. This instruction is similar to instruction 8 except that the branch address now

comes from the pipeline register rather than the file. In some cases, this instruction may be

thought of as a one-word file extension; that is, by using this instruction, a loop with the counter

can still be performed when subroutines are nested five deep. This instruction’s operation is very

similar to that of instruction 8. The differences are that on this instruction, a failed test condition

causes the source of the next microinstruction address to be the DIN inputs; and, when the test

condition is passed, this instruction does not perform a POP because the stack is not being used.

In the example of Figure II, the RPCT instruction is instruction 52 and is shown as a single

microinstruction loop. The address in the pipeline register would be 52. Instruction 51 in this

example could be the LOAD COUNTER AND CONTINUE instruction (number 12). While the

example shows a single microinstruction loop, by simply changing the address in a pipeline register,

multi-instruction loops can be performed in this manner for a fixed number of times as determined

by the counter.

Instruction 10 CRTN is the CONDITIONAL RETURN-FROM-SUBROUTINE instruction. As

the name implies, this instruction is used to branch from the subroutine back to the next

microinstruction address following the subroutine call. Since this instruction is conditional, the

return is performed only if the test is passed. If the test is failed, the next sequential

microinstruction is performed. The example in Figure II depicts the use of the CRTN instruction

in both the conditional and the unconditional modes. This example first shows a jump-to-

subroutine at instruction location 52 where control is transferred to location 90. At location 93, a

CRTN instruction is performed. If the test is passed, the stack is accessed and the program will