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L64250JC15 Datasheet(PDF) 7 Page - InnovASIC, Inc |
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L64250JC15 Datasheet(HTML) 7 Page - InnovASIC, Inc |
7 / 21 page IA64250 Data Sheet Histogram/Hough Transform Processor As of Production Ver. 01 Copyright © 2000 ENG211001219-01 www.innovasic.com innovASIC Customer Support: The End of Obsolescence ™ Page 7 of 21 1-888-824-4184 Mode Definition: The controller block decodes the instructions brought in to the IA64250 on the CI bus, with the REGADR input determining which instructions are being read in. The Mode Memory table shows the configuration of the CI bus encoded instruction depending on the state of REGADR. A brief description of the instruction bits follows: sel(3:0) selects the nine bits of the ACC RAM to be transferred to the DO output or to the LUT RAM. sel0 sel1 sel2 sel3 Sel window 0 1 0 1 0 … 1 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 1 2 3 4 15 select bits 0-8 select bits 1-9 select bits 2-10 select bits 3-11 select bits 4-12 select bits 15-23 lut(1:0) defines one of the four 512 X 9 LUTs as active. sh1 When low, the least significant nine bits of the 10 bit LUT and Y count sum will address the ACC RAM. When high, the nine most significant bits of the sum will be used. sat When high, the nine bits selected from the 24 bit ACC RAM output will be forced to 511 (111111111) if the 24 bit ACC RAM output contains a 1 in the range of bits from the sel + 9 to 23. Otherwise the nine bits selected from the ACC RAM output will be unchanged. test Used for testing when low. Should be high for normal operation. fn(1:0) Determines the operation performed during the computational mode. fn0 fn1 FUNCTION 0 0 1 1 0 1 0 1 modified Hough transform computation undefined histogram computation pixel location eq When high, causes the output of the ACC RAM to be accumulated as it is read. This is commonly used to compute the histogram equalization transfer function. When low, the ACC RAM output is not modified. |
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