Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

IA59032 Datasheet(PDF) 6 Page - InnovASIC, Inc

Part No. IA59032
Description  32-Bit High Speed Microprocessor Slice
Download  17 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  INNOVASIC [InnovASIC, Inc]
Homepage  http://www.innovasic.com
Logo 

IA59032 Datasheet(HTML) 6 Page - InnovASIC, Inc

Zoom Inzoom in Zoom Outzoom out
 6 / 17 page
background image
Page 6 of 17
IA59032
Data Sheet
32-Bit High Speed Microprocessor Slice
Copyright
© 2000
innovASIC
[_________The End of Obsolescence
The 32-bit data output field (Y) features three-state outputs. An output control (OEn) is used to enable the
three-state outputs. When OEn is HIGH, the Y outputs are in the high-impedance state.
A two input mux is also used at the data output such that either the A-port of the RAM or the ALU outputs
(F) are selected at the device Y outputs. I(8:6) inputs control this selection.
As was discussed previously, the RAM inputs are driven from a three-input mux. This allows the ALU
outputs to be entered non-shifted, shifted up one position (X2) or shifted down one position (/2). The
shifter has two ports; one is labeled RAM0 and the other is RAM31. Both of these ports consist of a buffer
driver with a three-state output and an input to the mux. Thus, in the shift up mode, the RAM31 buffer is
enabled and the RAM0 mux input is enabled. Likewise, is in the shift down mode, the RAM0 buffer and
RAM31 input are enabled. In the no-shift mode, both buffers are in the high-impedance state and the mux
inputs are not selected. The I(8:6) inputs control the shifter.
Similarly, the Q register is driven from a 3-input mux. In the no-shift mode, the mux enters the ALU data
into the Q register. In either the shift-up or shift-down mode, the mux selects the Q register data
appropriately shifted up or down. The Q shifter also has two ports; Q0 and Q31. The operations of these
two ports are similar to the RAM shifter and are also controlled from the I(8:6) inputs.
The clock input controls the RAM, Q register, and the A and B data latches. When enabled, data is clocked
into the Q register on the LOW to HIGH transition of the clock. When CP is HIGH, the A and B latches
are open and will pass whatever data is present at the RAM outputs. When CP is LOW, the latches are
closed and will retain the last data entered. New data will be written into the RAM defined by the B address
field when the clock input is LOW.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn