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ILC705 Datasheet(PDF) 3 Page - Impala Linear Corporation

Part No. ILC705
Description  MP SUPERVISORY CIRCUIT
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Maker  IMPALA [Impala Linear Corporation]
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ILC705 Datasheet(HTML) 3 Page - Impala Linear Corporation

   
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mP Supervisory Circuit
Impala Linear Corporation
3
(408) 574-3939
www.impalalinear.com
Sept 1999
ILC705-708 1.0
Pin Number
Pin
Name
ILC705
ILC706
ILC707
ILC708
Description
MR
1
1
Manual reset input. MR forces RESET to assert when pulled below 0.8V.
An internal pull-up current of 250 mA on this input forces it high when
left floating. This input can also be driven from TTL or CMOS logic.
Vcc
2
2
Power supply input, 5V.
GND
3
3
Ground pin, 0 V reference.
PFI
4
4
Power fail input. Internally connected to the power fail comparator, which
is referenced to 1.25V. The power fail output (PFO) remains high if PFI
is above 1.25V. PFI should be connected to GND or VOUT if the power
fail comparator is not used.
PFO
5
5
Power fail output. The power fail comparator is independent of all other
functions on this device.
WDI
6
N/A
Watchdog input. The WDI input monitors microprocessor activity, an
internal watchdog timer resets itself with each transition on the watchdog
input. If the WDI pin is held high or low for longer than the watchdog
timeout period, WDO is forced to active low. The watchdog function can
be disabled by floating the WDI pin.
N/C
N/A
6
No Connect.
RESET
7
7
RESET output. RESET is asserted if either VCC goes below the reset
threshold or by a low signal on the manual reset input (MR). RESET
remains asserted for one reset timeout period (200ms) after VCC
exceeds the reset threshold or after the manual reset pin transitions from
low to high. The watchdog timer will not assert RESET unless WDO is
connected to MR.
WDO
8
N/A
Watchdog timer output. The watchdog timer resets itself with each
transition on the watchdog input. If the WDI pin is held high or low for
longer than the watchdog timeout period, WDO is forced low. WDO will
also be forced low if VCC is below the reset threshold and will remain low
until VCC returns to a valid level.
RESET
N/A
8
RESET output. RESET is the compliment of RESET and is asserted if
either VCC goes below the reset threshold or by a low signal on the
manual reset input (MR). RESET is suitable for microprocessors
systems that use an active high reset.
Pin Functions


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