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AD1819B Datasheet(PDF) 7 Page - Analog Devices |
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AD1819B Datasheet(HTML) 7 Page - Analog Devices |
7 / 28 page AD1819B –7– REV. 0 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1819B features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS* Parameter Min Max Units Power Supplies Analog (AVDD) –0.3 6.0 V Digital (DVDD) –0.3 6.0 V Input Current (Except Supply Pins) ±10.0 mA Analog Input Voltage (Signal Pins) –0.3 AVDD + 0.3 V Digital Input Voltage (Signal Pins) –0.3 DVDD + 0.3 V Ambient Temperature (Operating) –40 +85 °C Storage Temperature –65 +150 °C *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Temperature Package Package Model Range Description Option* AD1819BJST –40 °C to +85°C 48-Terminal LQFP ST-48 *ST = Thin Quad Flatpack. ENVIRONMENTAL CONDITIONS Ambient Temperature Rating TAMB = TCASE – (PD × θ CA) TCASE = Case Temperature in °C PD = Power Dissipation in W θ CA = Thermal Resistance (Case-to-Ambient) θ JA = Thermal Resistance (Junction-to-Ambient) θ JC = Thermal Resistance (Junction-to-Case) Package JA JC CA LQFP 76.2 °C/W 17 °C/W 59.2 °C/W BIT_CLK SYNC tHOLD SDATA_OUT tSETUP Figure 4. Data Setup and Hold BIT_CLK SYNC SDATA_IN tRISECLK tRISESYNC tRISEDIN tRISEDOUT tFALLCLK tFALLSYNC tFALLDIN tFALLDOUT SDATA_OUT Figure 5. Signal Rise and Fall Time BIT_CLK SDATA_OUT SYNC SDATA_IN SLOT 1 SLOT 2 WRITE TO 0x26 DATA PR4 DON’T CARE tS2_PDOWN NOTE: BIT_CLK NOT TO SCALE Figure 6. AC-Link, Link Low Power Mode Timing RESET SDATA_OUT HI-Z tSETUP2RST tOFF SDATA_IN, BIT_CLK Figure 7. ATE Test Mode WARNING! ESD SENSITIVE DEVICE |
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