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ILC1832 Datasheet(PDF) 3 Page - Impala Linear Corporation

Part No. ILC1832
Description  μP SUPERVISORY CIRCUIT
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Maker  IMPALA [Impala Linear Corporation]
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ILC1832 Datasheet(HTML) 3 Page - Impala Linear Corporation

   
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Pin
Number
Pin
Name
Description
1
PBRST
Pushbutton reset input. This input is debounced and can be driven with external logic
signals or a mechanical pushbutton to actively force a reset. All pulses less than 1ms in
duration on the PBRST pin are ignored. Any pulse with a duration of 20ms or greater is
guaranteed to cause a reset. PBRST has an internal 40k
Ω (typical) pull-up resistor to V
CC.
2
TD
Time delay input. This input selects the timebase used by the watchdog timer. When TD =
0V, the watchdog timeout period is set to a nominal value of 150ms, when TD = open, the
watchdog timeout period is set to a nominal value of 600ms and when TD = VCC, the
watchdog timeout period is 1.2 sec nominally.
3
TOL
Tolerance select input. Selects whether 5% or 10% of VCC is used as the reset threshold
voltage. When TOL = 0V, the 5% tolerance level is selected and when TOL = VCC, a 10%
tolerance level is selected.
4
GND
Ground pin, 0V reference.
5
RST
RST is asserted high if either VCC goes below the reset threshold, the watchdog times out or
PBRST is pulled low for a minimum of 20ms. RST remains asserted for one reset timeout
period after VCC exceeds the reset threshold or after the watchdog times out or after PBRST
goes high.
6
RST
RST is asserted low if either VCC goes below the reset threshold, the watchdog times out or
PBRST is pulled low for a minimum of 20ms. RST remains asserted for one reset timeout
period after VCC exceeds the reset threshold or after the watchdog times out or after PBRST
goes high. Open-drain output.
7
ST
Input to the watchdog timer. If ST does not see a transition from high to low within the
watchdog timeout period, RST and RST will be asserted.
8
VCC
Power supply input.
8
1
Reset
Generator
6
4
-
+
VCC
ST
RST
GND
3
7
2
Trip Point
Select
Ref
Manual Reset
Debounce
Watchdog
Timer
Timeout
Select
5
RST
TOL
PBRST
TD
µP Supervisory Circuit
Preliminary
Pin Functions
Block Diagram
Impala Linear Corporation
3
(408) 574-3939
www.impalalinear.com
October 1999
ILC1832 1.1


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