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IDT54FCT841DTQ Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT54FCT841DTQ Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 7 page 6.22 2 MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT54/74FCT841AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES PIN CONFIGURATIONS 2571 drw 02 2571 drw 03 INDEX D2 Y2 Y3 Y4 NC Y5 LCC TOP VIEW 32 20 19 1 4 5 6 7 8 18 17 16 15 14 9 10 11 1213 L28-1 D3 D4 NC D5 D6 D7 Y6 Y7 21 22 23 24 25 26 27 28 OE D0 D1 D2 D3 D4 D5 D6 D7 GND Y0 Y1 Y2 Y3 Y4 Y6 LE Y5 Y7 VCC 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 P24-1 D24-1 SO24-2 SO24-7 SO24-8 & E24-1 11 12 21 22 23 24 D8 D9 Y8 Y9 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW PIN DESCRIPTION FUNCTION TABLE (1) 2571 tbl 01 NOTE: 2571 tbl 02 1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, Z = High Impedance ABSOLUTE MAXIMUM RATINGS (1) Symbol Rating Commercial Military Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7.0 –0.5 to +7.0 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC +0.5 –0.5 to VCC +0.5 V TA Operating Temperature 0 to +70 –55 to +125 °C TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 0.5 0.5 W IOUT DC Output Current –60 to +120 –60 to +120 mA 2571 lnk 03 CAPACITANCE (TA = +25 °C, f = 1.0MHz) NOTE: 1. This parameter is measured at characterization but not tested. 2571 lnk 04 Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. Name I/O Description DI I The latch data inputs. LE I The latch enable input. The latches are transparent when LE is HIGH. Input data is latched on the HIGH-to-LOW transition. YI O The 3-state latch outputs. OE I The output enable control. When OE is LOW, the outputs are enabled. When OE is HIGH, the outputs VI are in high- impedance (off) state. Inputs Internal Output OE OE LE DI QI YI Function H H L L Z High Z H H H H Z High Z H L X NC Z Latched (High Z) L H L L L Transparent L H H H H Transparent L L X NC NC Latched |
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