IDT54/74FCT88915TT 55/70/100/133

LOW SKEW PLL-BASED CLOCK DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.7

1

Integrated Device Technology, Inc.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• 0.5 MICRON CMOS Technology

• Input frequency range: 10MHz – f2Q Max. spec

(FREQ_SEL = HIGH)

• Max. output frequency: 133MHz

• Pin and function compatible with MC88915T

• 5 non-inverting outputs, one inverting output, one 2x

output, one

÷2 output; all outputs are TTL-compatible

• 3-State outputs

• Output skew < 500ps (max.)

• Duty cycle distortion < 500ps (max.)

• TTL level output voltage swing

• 64/–15mA drive at TTL output voltage levels

• Available in 28 pin PLCC, LCC and SSOP packages

1

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AUGUST 1995

©1995 Integrated Device Technology, Inc.

9.7

DSC-4247/1

is fed back to the PLL at the FEEDBACK input resulting in

essentially delay across the device. The PLL consists of the

phase/frequency detector, charge pump, loop filter and VCO.

The VCO is designed for a 2Q operating frequency range of

40MHz to f2Q Max.

The IDT54/74FCT88915TT provides 8 outputs with 500ps

skew. The Q5 output is inverted from the Q outputs. The 2Q

runs at twice the Q frequency and Q/2 runs at half the Q

frequency.

The FREQ_SEL control provides an additional

÷ 2 option in

the output path. PLL _EN allows bypassing of the PLL, which

is useful in static test modes. When PLL_EN is low, SYNC

input may be used as a test clock. In this test mode, the input

frequency is not limited to the specified range and the polarity

of outputs is complementary to that in normal operation

(PLL_EN = 1). The LOCK output attains logic HIGH when the

PLL is in steady-state phase and frequency lock. When OE/

RST is low, all the outputs are put in high impedance state and

registers at Q, Q and Q/2 outputs are reset.

The IDT54/74FCT88915TT requires one external loop

filter component as recommended in Figure 1.

IDT54/74FCT88915TT

55/70/100/133

PRELIMINARY

LOW SKEW PLL-BASED

CMOS CLOCK DRIVER

(WITH 3-STATE)

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The IDT54/74FCT88915TT uses phase-lock loop technol-

ogy to lock the frequency and phase of outputs to the input

reference clock. It provides low skew clock distribution for

high performance PCs and workstations. One of the outputs

Phase/Freq.

Detector

M

u

x

0

1

SYNC (0)

FEEDBACK

SYNC (1)

REF_SEL

PLL_EN

Mux

01

Divide

-By-2

(

÷1)

(

÷2)

1

0

M

u

x

Charge Pump

Voltage

Controlled

Oscilator

OE/RST

FREQ_SEL

2Q

Q0

Q1

Q2

Q3

Q4

Q5

Q/2

D

Q

CP

Q

R

D

Q

CP

Q

R

D

Q

CP

R

D

Q

CP

R

D

Q

CP

R

D

Q

CP

R

D

Q

CP

R

D

Q

CP

LF

LOCK

3072 drw 01