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IDT79R3051E-33MJ Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT79R3051E-33MJ Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 23 page  5.3 3 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE Figure 3. Virtual-to-Physical Mapping of Extended Architecture Versions Kernel Mapped (kseg2) Kernel Uncached (kseg1) Kernel Cached (kseg0) User Mapped Cacheable (kuseg) Physical Memory Memory 0xffffffff 0xc0000000 0xa0000000 0x80000000 0x00000000 3548MB 512MB Any Any VIRTUAL PHYSICAL 2874 drw 03 Figure 4. Virtual-to-Physical Mapping of Base Architecture Versions 1MB Kernel Rsvd Kernel Cacheable Tasks Kernel/User Cacheable Tasks Inaccessible Kernel Boot and I/O 0xffffffff 0xc0000000 0xa0000000 0x80000000 0x00000000 1024MB 2048MB 512MB 512MB VIRTUAL PHYSICAL Kernel Cached (kseg2) Kernel Uncached (kseg1) Kernel Cached (kseg0) User Cached (kuseg) 1MB User Rsvd 2874 drw 04 The base versions of the architecture (the IDT79R3051 and IDT79R3052) remove the TLB and institute a fixed address mapping for the various segments of the virtual address space. The base processors support distinct kernel and user mode operation without requiring page management software, leading to a simpler software model. The memory mapping used by these devices is illustrated in Figure 4. Note that the reserved address spaces shown are for compatibility with future family members; in the current family members, references to these addresses are translated in the same fashion as their respective segments, with no traps or excep- tions taken. When using the base versions of the architecture, the system designer can implement a distinction between the user tasks and the kernel tasks, without having to execute page management software. This distinction can take the form of physical memory protection, accomplished by ad- dress decoding, or in other forms. In systems which do not wish to implement memory protection, and wish to have the kernel and user tasks operate out of a single unified memory space, upper address lines can be ignored by the address decoder, and thus all references will be seen in the lower gigabyte of the physical address space. |
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