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IDT74FCT88915TT55LB Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT74FCT88915TT55LB Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 11 page IDT54/74FCT88915TT 55/70/100/133 LOW SKEW PLL-BASED CMOS CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES 9.7 10 TEST CIRCUITS AND WAVEFORM 50 Ω to VCC/2, CL = 20pF PROPAGATION DELAY, OUTPUT SKEW ENABLE AND DISABLE TEST CIRCUIT Pulse Generator R T D.U.T. VCC VIN C L V OUT 50pF 500 Ω 500 Ω 7.0V NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable- HIGH 2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns 3072 lnk 12 Pulse Generator RT D.U.T. VCC VIN VOUT 100 Ω 100 Ω VCC 20pF 3072 drw 11 NOTES: 1. The FCT88915TT aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the 1.5V crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation around a center point. 3. If a Q output is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice the SYNC frequency and the Q/2 output would run at half the SYNC frequency. (These waveforms represent the hookup of Figure 2a) t t t t tPD SYNC INPUT (SYNC (1) or SYNC (0)) FEEDBACK INPUT Q/2 OUTPUT Q0-Q4 OUTPUTS Q5 OUTPUT 2Q OUTPUT tSKEWALL SKEWf SKEWr SKEWf SKEWr t "Q" OUTPUTS CYCLE 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V 3072 drw 13 t CYCLE SYNC INPUT Test Switch Disable Low Enable Low Closed Disable High Enable High Open DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 3072 tbl 10 CONTROL INPUT 3V 1.5V 0V 3.5V 0V OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED SWITCH OPEN VOL VOH 0.3V 0.3V t PLZ tPZL tPZH t PHZ 0V 1.5V 1.5V ENABLE DISABLE ENABLE AND DISABLE TIMES SWITCH POSITION 3072 drw 14 |
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