Electronic Components Datasheet Search |
|
IDT79R3051E-25MJ Datasheet(PDF) 10 Page - Integrated Device Technology |
|
IDT79R3051E-25MJ Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 23 page 5.3 10 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (Continued): PIN NAME I/O DESCRIPTION Burst/ O Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current bus read WrNear is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles due to cache misses; it is asserted for all I-Cache miss read cycles, and for D-Cache miss read cycles if selected at device reset time. On write transactions, the WrNear output tells the external memory system that the bus interface unit is performing back-to-back write transactions to an address within the same 256 word page as the prior write transaction. This signal is useful in memory systems which employ page mode or static column DRAMs, and allows near writes to be retired quickly. Rd O Read: An output which indicates that the current bus transaction is a read. Wr O Write: An output which indicates that the current bus transaction is a write. Ack I Acknowledge: An input which indicates to the device that the memory system has sufficiently processed the bus transaction, and that the CPU may either terminate the write cycle or process the read data from this read transfer. RdCEn I Read Buffer Clock Enable: An input which indicates to the device that the memory system has placed valid data on the A/D bus, and that the processor may move the data into the on-chip Read Buffer. SysClk O System Reference Clock: An output from the CPU which reflects the timing of the internal processor "Sys" clock. This clock is used to control state transitions in the read buffer, write buffer, memory controller, and bus interface unit. BusReq I DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus interface signals so that they may be driven by an external master. BusGnt O DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has been detected, and that the bus is relinquished to the external master. SBrCond(3:2) I Branch Condition Port: These external signals are internally connected to the CPU signals BrCond(1:0) CpCond(3:0). These signals can be used by the branch on co-processor condition instructions as input ports. There are two types of Branch Condition inputs: the SBrCond inputs have special internal logic to synchronize the inputs, and thus may be driven by asynchronous agents. The direct Branch Condition inputs must be driven synchronously. BErr I Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error. This signal is only sampled during read and write operations. If the bus transaction is a read operation, then the CPU will take a bus error exception. Int(5:3) I Processor Interrupt: During normal operation, these signals are logically the same as the Int(5:0) SInt(2:0) signals of the R3000. During processor reset, these signals perform mode initialization of the CPU, but in a different (simpler) fashion than the interrupt signals of the R3000. There are two types of interrupt inputs: the SInt inputs are internally synchronized by the processor, and may be driven by an asynchronous external agent. The direct interrupt inputs are not internally synchronized, and thus must be externally synchronized to the CPU. The direct interrupt inputs have one cycle lower latency than the synchronized interrupts. Clk2xIn I Master Clock Input: This is a double frequency input used to control the timing of the CPU. Reset I Master Processor Reset: This signal initializes the CPU. Mode selection is performed during the last cycle of Reset. Rsvd(4:0) I/O Reserved: These five signal pins are reserved for testing and for future revisions of this device. Users must not connect these pins. 2874 tbl 03 |
Similar Part No. - IDT79R3051E-25MJ |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |