Electronic Components Datasheet Search |
|
IDT79RV4650-267DP Datasheet(PDF) 9 Page - Integrated Device Technology |
|
IDT79RV4650-267DP Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 25 page 9 of 25 March 28, 2000 IDT79RC4650™ The following is a list of the supported external requests: x Read Response x Null %RRW07LPH#2SWLRQV %RRW07LPH#2SWLRQV %RRW07LPH#2SWLRQV %RRW07LPH#2SWLRQV Fundamental operational modes for the processor are initialized by the boot-time mode control interface. The boot-time mode control inter- face is a serial interface operating at a very low frequency (MasterClock divided by 256). The low-frequency operation allows the initialization information to be kept in a low-cost EPROM; alternatively the twenty-or- so bits could be generated by the system interface ASIC or a simple PAL. To initialize all fundamental, operational modes, immediately after the VCCOK signal is asserted, the processor reads a serial bit stream of 256 bits. After initialization is complete, the processor continues to drive the serial clock output, but no further initialization bits are read. %RRW07LPH#0RGHV %RRW07LPH#0RGHV %RRW07LPH#0RGHV %RRW07LPH#0RGHV The boot-time serial mode stream is defined in Table 5. Bit 0 is the bit presented to the processor when VCCOK is asserted; bit 255 is the last. 3RZHU#0DQDJHPHQW 3RZHU#0DQDJHPHQW 3RZHU#0DQDJHPHQW 3RZHU#0DQDJHPHQW CP0 is also used to control the power management for the RC4650. This is the standby mode and it can be used to reduce the power consumption of the internal core of the CPU. The standby mode is entered by executing the WAIT instruction with the SysAD bus idle and is exited by any interrupt. 6WDQGE\#0RGH#2SHUDWLRQ 6WDQGE\#0RGH#2SHUDWLRQ 6WDQGE\#0RGH#2SHUDWLRQ 6WDQGE\#0RGH#2SHUDWLRQ The RC4650 provides a means to reduce the amount of power consumed by the internal core when the CPU would otherwise not be performing any useful operations. This is known as “Standby Mode.” (QWHULQJ#6WDQGE\#0RGH (QWHULQJ#6WDQGE\#0RGH (QWHULQJ#6WDQGE\#0RGH (QWHULQJ#6WDQGE\#0RGH Executing the WAIT instruction enables interrupts and enters Standby mode. When the WAIT instruction finishes the W pipe-stage, if the SysAd bus is currently idle, the internal clocks will shut down, thus freezing the pipeline. The PLL, internal timer, and some of the input pins (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run. If the conditions are not correct when the WAIT instruction finishes the W pipe-stage (i.e. the SysAd bus is not idle), the WAIT is treated as a NOP. Once the CPU is in Standby Mode, any interrupt, including the inter- nally generated timer interrupt, will cause the CPU to exit Standby Mode. 7KHUPDO#&RQVLGHUDWLRQV 7KHUPDO#&RQVLGHUDWLRQV 7KHUPDO#&RQVLGHUDWLRQV 7KHUPDO#&RQVLGHUDWLRQV The RC4650 utilizes special packaging techniques to improve the thermal properties of high-speed processors. The RC4650 is packaged using cavity down packaging in a 208-pin QFP (DP). The QFP package allows for an efficient thermal transfer between the die and the case. The R4650 and the RV4650 are guaranteed in a case temperature range of 0 °C to +85°C for commercial temperature parts and in a case temperature range of -40 °C to +85°C for industrial temperature parts. The type of package, speed (power) of the device, and airflow conditions affect the equivalent ambient temperature conditions that will meet this specification. The equivalent allowable ambient temperature, TA, can be 0RGH#ELW 'HVFULSWLRQ 255..15 Must be zero 14..13 Output driver strength: 10 → 100% strength (fastest) 11 → 83% strength 00 → 67% strength 01 → 50% strength (slowest) 11 Disable the timer interrupt on Int[5] 12 0 → 64-bit system interface 1 → 32-bit system interface 10..9 00 → RC4000 compatible 01 → reserved 10 → pipelined writes 11 → write re-issue 80 → Little endian 1 → Big endian 7..5 Clock multiplier: 0 → 2 1 → 3 2 → 4 3 → 5 4 → 6 5 → 7 6 → 8 7 reserved 4..1 Writeback data rate: 64-bit 0 → ∆ 1 → DDx 2 → DDxx 3 → DxDx 4 → DDxxx 5 → DDxxxx 6 → DxxDxx 7 → DDxxxxxx 8 → DxxxDxxx 9-15 reserved 32-bit 0 → Ω 1 → WWx 2 → WWxx 3 → WxWx 4 → WWxxx 5 → WWxxxx 6 → WxxWxx 7 → WWxxxxxx 8 → WxxxWxxx 9-15 reserved 0 Reserved (must be zero) Table 5 Boot-time mode stream |
Similar Part No. - IDT79RV4650-267DP |
|
Similar Description - IDT79RV4650-267DP |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |