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IDT79RV4640-100DUI Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT79RV4640-100DUI Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 23 page 7 of 23 April 10, 2001 IDT79RC4640™ Boot-Time Options Boot-Time Options Boot-Time Options Boot-Time Options ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses between the processor and an external device. When an external device needs to control the interface, it asserts ExtRqst*. The RC4640 responds by asserting Release* to release the system interface to slave state. ValidOut* and ValidIn* are used by the RC4640 and the external device respectively to indicate that there is a valid command or data on the SysAD and SysCmd buses. The RC4640 asserts ValidOut* when it is driving these buses with a valid command or data, and the external device drives ValidIn* when it has control of the buses and is driving a valid command or data. Non-overlapping System Interface Non-overlapping System Interface Non-overlapping System Interface Non-overlapping System Interface The RC4640 requires a non-overlapping system interface, compat- ible with the RC4700. This means that only one processor request may be outstanding at a time and that the request must be serviced by an external device before the RC4640 issues another request. The RC4640 can issue read and write requests to an external device, and an external device can issue read and write requests to the RC4640. The RC4640 asserts ValidOut* and simultaneously drives the address and read command on the SysAD and SysCmd buses. If the system interface has RdRdy* or Read transactions asserted, then the processor tristates its drivers and releases the system interface to slave state by asserting Release*. The external device can then begin sending the data to the RC4640. Fundamental operational modes for the processor are initialized by the boot-time mode control interface. The boot-time mode control inter- face is a serial interface operating at a very low frequency (MasterClock divided by 256). The low-frequency operation allows the initialization information to be kept in a low-cost EPROM; alternatively the twenty-or- so bits could be generated by the system interface ASIC or a simple PAL. Immediately after the VCCOK Signal is asserted, the processor reads a serial bit stream of 256 bits to initialize all fundamental opera- tional modes. After initialization is complete, the processor continues to drive the serial clock output, but no further initialization bits are read. Boot-Time Modes Boot-Time Modes Boot-Time Modes Boot-Time Modes The boot-time serial mode stream is defined in Table 6. Bit 0 is the bit presented to the processor when VCCOK is asserted; bit 255 is the last. Power Management Power Management Power Management Power Management CP0 is also used to control the power management for the RC4640. This is the standby mode and it can be used to reduce the power consumption of the internal core of the CPU. The standby mode is entered by executing the WAIT instruction with the SysAD bus idle and is exited by any interrupt. Standby Mode Operation Standby Mode Operation Standby Mode Operation Standby Mode Operation The RC4640 provides a means to reduce the amount of power consumed by the internal core when the CPU would otherwise not be performing any useful operations. This is known as “Standby Mode”. Entering Standby Mode Entering Standby Mode Entering Standby Mode Entering Standby Mode Executing the WAIT instruction enables interrupts and enters Standby mode. When the WAIT instruction finishes the W pipe-stage, if the SysAd bus is currently idle, the internal clocks will shut down, thus freezing the pipeline. The PLL, internal timer, and some of the input pins (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run. Figure 2 Typical RC4640 System Architecture RV4640 Memory I/O Controller Control Address SCSI ENET 32 9 Boot ROM DRAM (80ns) 2 11 |
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