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IDT54FCT841BDB Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT54FCT841BDB Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 7 page  7.22 2 IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS OE D0 D1 D2 D3 D4 D5 D6 D7 GND Y0 Y1 Y2 Y3 Y4 Y6 LE Y5 Y7 VCC P24-1 D24-1 E24-1 & SO24-2 D8 D9 Y8 Y9 DIP/CERPACK/SOIC TOP VIEW INDEX D2 Y2 Y3 Y4 NC Y5 LCC TOP VIEW L28-1 D3 D4 NC D5 D6 D7 Y6 Y7 32 20 19 1 4 5 6 7 8 18 17 16 15 14 9 10 11 12 13 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 11 12 21 22 23 24 2607 drw 02 2607 drw 03 PIN DESCRIPTION FUNCTION TABLE (1) Name I/O Description CLR I When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. DI I The latch data inputs. LE I The latch enable input. The latches are transparent when LE is HIGH. Input data is latched on the HIGH-to-LOW transition. YI O The 3-state latch outputs. OE I The output enable control. When OE is LOW, the outputs are enabled. When OE is HIGH, the outputs (Y I) are in the high-impedance (off) state. PRE I Preset line. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR. 2607 tbl 01 Inputs Inter- nal Out- puts CLR CLR PRE PRE OE OE LE DI QI YI Function H H H X X X Z High Z H H H H L L Z High Z H H H H H H Z High Z H H H L X NC Z Latched (High Z) H H L H L L L Transparent H H L H H H H Transparent H H L L X NC NC Latched H L L X X H H Preset L H L X X L L Clear L L L X X H H Preset L H H L X L Z Latched (High Z) H L H L X H Z Latched (High Z) NOTE: 2607 tbl 02 1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, Z = High Impedance |
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