IDT7MP4060/7MP4095

128K x 32 CMOS STATIC RAM MODULES

COMMERCIAL TEMPERATURE RANGE

7.09

6

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

WE

WE CONTROLLED TIMING)

(1, 2, 3, 7)

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CS

CS CONTROLLED TIMING)

(1, 2, 3, 5)

NOTES:

1.

WE or CS must be high during all address transitions.

CS and a low WE.

CS or WE going high to the end of write cycle.

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the

CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.

6. Transition is measured

±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.

7.

If

CS

3147 drw 08

ADDRESS

WE

DATA VALID

CS

3147 drw 07

ADDRESS

WE

(6)

(6)

(4)

(4)

(7)

(6)

OE

(6)

DATA VALID