IDT7MP4045/7MP4145

256K x 32 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

15.2

6

CS

2703 drw 10

ADDRESS

WE

(6)

(4)

(4)

(7)

OE

(6)

(6)

DATA VALID

(6)

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

WE

CS

2703 drw 11

ADDRESS

WE

DATA VALID

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CS

NOTES:

1.

WE or CS must be HIGH during all address transitions.

CS and a LOW WE.

CS or WE going HIGH to the end of write cycle.

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the

CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured

±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.

7. If

OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can