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IDT7M1002S45GB Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT7M1002S45GB Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 12 page IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES 7.02 7 TIMING WAVEFORM OF WRITE CYCLE NO. 2 ( CS CS CS CS CS CONTROLLED TIMING)(1, 2, 4) 2795 drw 07 DATAOUT tAW tDW DATAIN CS OE ADDRESS tWC tDH tCHZ tAS (6) tWP (2) tWR (7) tWHZ (9) OW t (9) (4) (4) DATA VALID R/ W (9) 2795 drw 08 tAW tDW DATAIN R/ W CS ADDRESS tWC tDH tAS (6) tWP (2) tWR (7) DATA VALID NOTES: 1. R/ W must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW R/W. 3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must be applied. 5. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. 6. Timing depends on which enable signal is asserted last. 7. Timing depends on which enable signal is de-asserted first. 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/ W W W W W CONTROLLED TIMING)(1, 2, 4) |
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