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IDT7MP4120S20Z Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7MP4120S20Z Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 8 page IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE FEATURES • High-density 4MB Static RAM module • Low profile 72-pin ZIP (Zig-zag In-line vertical Package) or 72-pin SIMM (Single In-line Memory Module) • Fast access time: 20ns (max.) • Surface mounted plastic components on an epoxy laminate (FR-4) substrate • Single 5V ( ±10%) power supply • Multiple GND pins and decoupling capacitors for maxi- mum noise immunity • Inputs/outputs directly TTL-compatible DESCRIPTION The IDT7MP4120 is a 1M x 32 Static RAM module con- structed on an epoxy laminate (FR-4) substrate using 8 1M x 4 Static RAMs in plastic packages. Availability of four chip select lines (one for each group of two RAMs) provides byte access. The IDT7MP4120 is available with access time as fast as 20ns with minimal power consumption. The IDT7MP4120 is packaged in a 72-pin FR-4 ZIP (Zig- zag In-line vertical Package)or a 72-pin SIMM (Single In-line Memory Module). The ZIP configuration allows 72 pins to be placed on a package 4.05" long and 0.365" wide. At only 0.60" high, this low-profile package is ideal for systems with mini- mum board spacing while the SIMM configuration allows use of edge mounted sockets to secure the module. All inputs and outputs of the IDT7MP4120 are TTL-com- patible and operate from a single 5V supply. Full asynchro- nous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use. Four identification pins (PD0, PD1, PD2 and PD3) are pro- vided for applications in which different density versions of the module are used. In this way, the target system can read the respective levels of PD0, PD1, PD2 and PD3 to determine a 1M depth. The contact pins are plated with 100 micro-inches of nickel covered by 30 micro-inches minimum of selective gold. COMMERCIAL TEMPERATURE RANGE SEPTEMBER 1996 ©1996 Integrated Device Technology, Inc. DSC-3019/5 7.07 1 PIN CONFIGURATION(1) 3019 drw 01 ZIP, SIMM TOP VIEW NOTE: 1. Pins 3, 4, 6 and 7 (PD0, PD1, PD2 and PD3 respectively) are read by the user to determine the density of the module. If PD0 reads GND, PD1 reads NC, PD2 reads GND and PD3 reads NC, then the module has a 1M depth. The IDT logo is a registered trademark of Integrated Device Technology Inc. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 NC PD2 GND PD1 I/O 8 I/O 9 I/O 10 I/O 11 A0 A1 A2 I/O 12 I/O 13 I/O 14 I/O 15 GND A15 CS2 CS4 A17 OE I/O 24 I/O 25 I/O 26 I/O 27 A3 A4 A5 VCC A6 I/O 28 I/O 29 I/O 30 I/O 31 A18 NC NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 CS3 A16 GND I/O 16 I/O 17 I/O 18 I/O 19 A10 A11 A12 A13 I/O 20 I/O 21 I/O 22 I/O 23 GND A19 NC PD0 -GND PD1 -NC PD2 -GND PD3 -NC PIN NAMES I/O0–I/O31 Data Inputs/Outputs A0–A19 Addresses CS1–CS4 Chip Selects WE Write Enable OE Output Enable PD0–PD3 Depth Identification VCC Power GND Ground NC No Connect 3019 tbl 01 WE 3019 drw 02 8 20 8 8 8 3 CS1 CS2 CS3 CS4 A0 – A19 I/O0-7 PD0 – PD3 1M x 32 RAM I/O8-15 I/O16-23 I/O24-31 OE FUNCTIONAL BLOCK DIAGRAM Integrated Device Technology, Inc. |
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