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IDT7M1002S35GB Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT7M1002S35GB Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 12 page  7.02 6 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE (1, 2, 4) 2795 drw 05 tAA tOH tRC ADDRESS DATAOUT tOH DATA VALID PREVIOUS DATA VALID 2795 drw 06 CURRENT 50% 50% DATA VALID tACE tAOE tCHZ (6) tOHZ (6) tPD (6) tPU (6) tCLZ (6) DATAOUT ICC ISB tSOP OE CS tSOP tOLZ (6) TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE (1, 3, 5) NOTES: 1. R/ W is HIGH for Read Cycles 2. Device is continuously enabled CS ≤ VIL. This waveform cannot be used for semaphore reads. 3. Addresses valid prior to or coincident with CS transition LOW. 4. OE ≤ VIL 5. To access RAM, CS ≤ VIL and SEM ≥ VIH. To access semaphore, CS ≥ VIH and SEM ≤ VIL. 6. This parameter is guaranteed by design but not tested. |
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