IDT7M1002S30GB datasheet(5/12 Pages) IDT

Part #	IDT7M1002S30GB

Description	16K x 32 CMOS DUAL-PORT STATIC RAM MODULE

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Manufacturer	IDT [Integrated Device Technology]

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IDT7M1002

16K x 32 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7.02

5

AC ELECTRICAL CHARACTERISTICS

(VCC = 5V

± 10%, TA = 55°C to +125°C or 0°C to +70°C)

7M1002SxxG

7M1002SxxGB

30

–35

–40

–45

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Unit

2795 tbl 10

Write Cycle (continued)

tDW

Data Valid to End-of-Write

22

—

25

—

25

—

25

—

ns

tDH

Data Hold Time

0

—

0

—

0

—

0

—

ns

tHZ

(1)

Output to High-Z

—

15

—

15

—

17

—

20

ns

tOW

(1)

Output Active from End-of-Write

0

—

0

—

0

—

0

—

ns

tSWRD

SEM Flag Write to Read Time

10

—

10

—

10

—

10

—

ns

tSPS

SEM Flag Contention Window

10

—

10

—

10

—

10

—

ns

Busy Cycle-Master Mode

(3)

tBAA

BUSY Access Time to Address

—

30

—

35

—

35

—

35

ns

tBDA

BUSY Disable Time to Address

—

25

—

30

—

30

—

30

ns

tBAC

BUSY Access Time to Chip Select

—

25

—

30

—

30

—

30

ns

tBDC

BUSY Disable Time to Chip Deselect

—

25

—

25

—

25

—

25

ns

tWDD(5)

Write Pulse to Data Delay

—

55

—

60

—

65

—

70

ns

tDDD

Write Data Valid to Read Data Delay

—

40

—

45

—

50

—

55

ns

tAPS

(6)

Arbitration Priority Set-Up Time

5

—

5

—

5

—

5

—

ns

tBDD

BUSY Disable to Valid Time

—

NOTE 9

—

NOTE 9

—

NOTE 9

—

NOTE 9

ns

Busy Cycle-Slave Mode

(4)

tWB

(7)

Write to BUSY Input

0

—

0

—

0

—

0

—

ns

tWH

(8)

Write Hold after BUSY

25

—

25

—

25

—

25

—

ns

tWDD

(5)

Write Pulse to Data Delay

—

55

—

60

—

65

—

70

ns

Interrupt Timing

tAS

Address Set-Up Time

0

—

0

—

0

—

0

—

ns

tWR

Write Recovery Time

0

—

0

—

0

—

0

—

ns

tINS

Interrupt Set Time

—

25

—

30

—

32

—

35

ns

tINR

Interrupt Reset Time

—

25

—

30

—

32

—

35

ns

NOTES:

1. This parameter is guaranteed by design but not tested.

2. To access RAM,

CS ≤ VIL and SEM ≥ VIH. To access semaphore, CS ≥ VIH and SEM ≤ VIL.

3. When the module is being used in the Master Mode (M/

S ≥ VIH).

4. When the module is being used in the Slave Mode (M/

S ≤ VIL).

5. Port-to-Port delay through the RAM cells from the writing port to the reading port.

6. To ensure that the earlier of the two ports wins.

7. To ensure that the write cycle is inhibited during contention.

8. To ensure that a write cycle is completed after contention.

9. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tDDD - tWP (actual).

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